[llvm-dev] Disable spilling sub-registers in LLVM

[ahmede via llvm-dev]

Hi Matthias,

No. I want the register allocator to spill the super-register (the large 
one e.g., 64-bit) and not just the sub-register (e.g., the 32-bit that 
is a piece of of the 64-bit register) because the stack loads/store 
width is 64-bit in this example.

RegClass1   (sub-registers):  sub_registers (32-bit)               --> 
can be natively used in arithmetic operations but no stack loads/stores 
for that width.

RegClass2 (super-registers):  [sub_register, subregister] (64-bit)  --> 
can be natively used in arithmetic operations and can be used in 
loads/stores.


Thanks,
Ahmed


On 2018-01-29 20:20, Matthias Braun wrote:
>> On Jan 29, 2018, at 1:20 PM, ahmede via llvm-dev 
>> <llvm-dev at lists.llvm.org> wrote:
>> 
>> Hi,
>> 
>> 
>> I wonder if there is a way in LLVM to disable spilling a 
>> register-class while still enabling the super-registers of this 
>> register-class to be spilled.
> What would you have the register allocator do when it runs out of
> register and you have spilling disabled? Abort the compilation?
> 
> If you just want a special instruction sequence (like using a bigger
> loads/stores for the spills) then you should be able to implement that
> in storeRegToStackSlot()/loadRegFromStackSlot().
> 
> - Matthias
> 
>> 
>> If not, how can we implement spilling for sub-registers when stack 
>> load/stores can only operate on the super registers? Is there a way 
>> even if it is suboptimal?
>> 
>> 
>> Thanks,
>> Ahmed
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