[llvm-dev] How to use tablegen to describe branches where the status register is implicitly set?

[Ahmed Samara via llvm-dev]

I'm working on writing a backend for a processor that only has one Branch
instruction, a BRnzp, where it branches on a status register (NZP:
Negative, Zero, Positive) based on what the result of the last arithmetic
operation was. It's implicitly set, nowhere in userspace.

Basically, it follows the format of:
ADD ....
BR 010  ... (Branches if the result of the ADD was zero).

Unconditional branches are given as a 111 argument.

How can I use tablegen to describe this in a way that the scheduler also
understands that it's 'attached' to the last instruction?

-- 
Ahmed Samara
M.S. Computer Engineering
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180129/bcba46f2/attachment.html>