[llvm-dev] Does it make sense to upstream some MVT's?

[Sean Silva via llvm-dev]

Hi,

Our backend for Pixel Visual Core uses some MVT's that aren't upstream.
Does it make sense to upstream them? I figure that as architectures get
wider, we'll eventually have "all" possible combinations of widths and
types, but on the other hand having code that isn't used by current
backends in tree isn't great.

These are the MVT's that we have added:

16x16 element (2D SIMD) 1-bit predicate registers:
v256i1

16x16 element (2D SIMD) 16-bit registers:
v256i16

20x20 element (2D SIMD) 16-bit registers: (we round up to v512 instead of
v400):
v512i16

32-bit versions of the above 16-bit registers (to represent 32-bit
accumulators for MAD instructions and also dual-issue "wide" instructions
to the dual non-MAD ALU's in each lane)
v256i32
v512i32


For those interested in more details about Pixel Visual Core, the 6th
edition of Hennessy and Patterson's "Computer Architecture: A Quantitative
Approach" http://a.co/et2K1xk has a section about it (Section 7.7 pg
579-592). I'll bring my copy to the next Bay Area LLVM Social if folks want
to take a look.

-- Sean Silva
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