[llvm-dev] Suggestions on code generation for SIMD

[serge guelton via llvm-dev]

On Tue, Jan 09, 2018 at 08:59:17PM -0800, Linchuan Chen wrote:
> Thanks Serge! This means for every new intrinsic set, a systematic change
> should be made to LLVM to support the new intrinsic set, right? The change
> should include frontend change, IR instruction set change, as well as low level
> code generation changes?

It really depends. In most cases, the intrinsic is implemented in terms
of generic vector instruction, directly represented at the LLVM level:

    static __inline __m256d __DEFAULT_FN_ATTRS
    _mm256_sub_pd(__m256d __a, __m256d __b)
    {
      return (__m256d)((__v4df)__a-(__v4df)__b);
    }

But some intrinsics cn not be modeled that way:


    static __inline __m256d __DEFAULT_FN_ATTRS
    _mm256_hadd_pd(__m256d __a, __m256d __b)
    {
      return (__m256d)__builtin_ia32_haddpd256((__v4df)__a, (__v4df)__b);
    }

In that case, the builtin is relatively opaque to the Middle End, nd
lowered in the backend (see include/llvm/IR/IntrinsicsX86.td)