[llvm-dev] [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported?

[Ulrich Weigand via llvm-dev]

Andrew Kaylor wrote:

>In general, the current "strict FP" handling stops at instruction
>selection. At the MachineIR level we don't currently have a mechanism
>to prevent inappropriate optimizations based on floating point
>constraints, or indeed to convey such constraints to the backend.
>Implicit register use modeling may provide some restriction on some
>architectures, but this is definitely lacking for X86 targets. On the
>other hand, I'm not aware of any specific current problems, so in many
>cases we may "get lucky" and have the correct thing happen by chance.
>Obviously that's not a viable long term solution. I have a rough plan
>for adding improved register modeling to the X86 backend, which should
>take care of instruction scheduling issues, but we'd still need a
>mechanism to prevent constant folding optimizations and such.

Given that Kevin intends to target SystemZ, I'll be happy to work on the
SystemZ back-end support for this feature.  I agree that we should be using
implicit control register dependencies, which will at least prevent moving
floating-point operations across instructions that e.g. change rounding
modes.   However, the main property we need to model is that floating-point
operations may *trap*.   I guess this can be done using
UnmodeledSideEffects, but I'm not quite clear on how to make this dependent
on whether or not a "strict" operation is requested (without duplicating
all the instruction patterns ...).

Once we do use something like UnmodeledSideEffects, I think MachineIR
passes should handle everything correctly; in the end, the requirements are
not really different from those of other trapping instructions.  B.t.w. I
don't think anybody does constant folding on floating-point constants at
the MachineIR level anyway ... have you seen this anywhere?


Mit freundlichen Gruessen / Best Regards

Ulrich Weigand

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