[llvm-dev] similar instructions with disjoint register files

[Davis, Alan via llvm-dev]

I'm working on a backend for a target with multiple functional units, each with a dedicated register file. Several instructions can operate on any one of the functional units. For example there is an add instruction on the A unit that adds two A registers, and another on the D unit that adds two D registers, but neither can use the other's registers. From a selection point of view either could be used for a 32-bit add, but the encoding and pipeline behavior is different. I was thinking of modeling this as a pseudo instruction that could represent either form and then get rewritten after register allocation. The first question is: is there a way to model register constraints that tie multiple registers to one of several classes, i.e. as "all operands must be from either the A class or D class (but not mixed)"?

Beyond that, I was thinking to have a heuristic-based pass between instruction selection and register allocation to choose a functional unit based on some context, then constrain the registers based on the functional unit assignment. Does that sound reasonable?

Are there any targets that do something similar to either of these techniques?

-Alan
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