[llvm-dev] RegBankSelect complex value mappings

Quentin Colombet via llvm-dev llvm-dev at lists.llvm.org
Thu Dec 20 16:15:18 PST 2018

Hi Matt,

Your use case falls definitely in what RegBankSelect meant to solve.
That said, the support you need is not implemented because we didn't
have use cases to test the code against.

Regarding the cost, if the mapping produces more than 1 partial value,
right now RegBankSelect::getRepairCost will say this is too expensive
and this is actually where you need to patch the pass to add a target
hook to compute something that would use instruction to decompose the

Le mer. 19 déc. 2018 à 21:25, Matt Arsenault <arsenm2 at gmail.com> a écrit :
> Hi,
> I’m looking at RegBankSelect’s partially implemented support for deciding to split a value between multiple registers and I’m wondering if it’s actually intended to solve the problem I’m trying to use it for. RegisterBankInfo.h has this example mapping table:
>   /// E.g.,
>   /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
>   /// can expand the
>   /// <2 x 32-bit> add into 2 x 32-bit add.
>   ///
>   /// Currently the TableGen-like file would look like:
>   /// \code
>   /// PartialMapping[] = {
>   /// /*32-bit add*/ {0, 32, GPR},
>   /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
>   /// /*<2x32-bit> vadd {0, 64, VPR}
>   /// }; // PartialMapping duplicated.
>   ///
>   /// ValueMapping[] {
>   ///   /*plain 32-bit add*/ {&PartialMapping[0], 1},
>   ///   /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
>   ///   /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
>   /// };
> This looks almost like the problem I want to solve for AMDGPU. There are 2 main register banks. On the SALU, some 64-bit operation are available which can only be 32-bit on the VALU. For example, if all of the input operands aren’t in the scalar bank, a 64-bit and needs to be split into 2 32-bit ands. It’s illegal to copy from the vector to the scalar bank, since these don’t mean what vector and scalar mean on other targets.
> The current code seems very operand centric and computes costs only based on copies. Decomposing the operation into 2 pieces requires rewriting the entire instruction,

So the copy part cost I covered it. For the cost of rewriting the
instruction completely, this is captured by
The idea of InstructionMapping::getCost is to reflect the cost for
transforming the current instruction into the instruction after we
apply this mapping. Then the RepairCost is here to account for the
cost of "bringing" every operand to the right place for this mapping
using copy or some target specific sequence.
Like the cost computation, the target specific sequences are not
implemented, but should happen in RegBankSelect::repairReg. Right now,
this will assert that the number of break downs should be == 1 but the
code to decompose the operand should happen there.
Finally, the rewriting of the current instruction is supposed to
happen in RegisterBankInfo::applyMapping.

If you have an example (.mir) that you can share, we can work together
to make this happen.


> not just copying from one offending operand. Is this intended to handle this kind of case, or do I need to introduce a separate register bank aware legalizer pass?
> -Matt

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