[llvm-dev] MC Assembler / tablegen: actually parsing variable_ops

Wouter van Oortmerssen via llvm-dev llvm-dev at lists.llvm.org
Mon Dec 10 14:18:14 PST 2018

Thanks! I'm adopting what ARM does for WebAssembly, and it appears to work

On Mon, Dec 3, 2018 at 5:51 PM Friedman, Eli <efriedma at codeaurora.org>

> On 12/3/2018 5:32 PM, Wouter van Oortmerssen via llvm-dev wrote:
> > variable_ops is used in the tablegen defs for many targets to denote
> > instructions that a variable number of inputs, but it seems that there
> > aren't any targets for which this results in variable elements in the
> > instruction encoding (and thus in assembler parsing), since the
> > tablegen generated assembly matcher ($(Target)GenAsmMatcher.inc)
> > simply assumes that variable_ops are not to be parsed (match table:
> > Convert_NoOperands).
> ARM has ldm/stm, which take a variable number of register operands.  You
> might want to look at how ARMInstrInfo.td uses a "reglist" operand to
> represent the list of registers.
> -Eli
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux
> Foundation Collaborative Project
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20181210/118e744a/attachment.html>

More information about the llvm-dev mailing list