[llvm-dev] A way to opt out of a dag combine?

[Jon Chesterfield via llvm-dev]

Is there an established way of disabling a DAG combine on a per target
basis, where it appears to be detrimental to the generated code? Writing if
(!mytarget) in DAGCombiner.cpp works but tends to be erased by git merge
and generally doesn't look ideal. Writing the inverse transform in target
specific code doesn't work in this instance and in general creates an
infinite loop.


Guidance would be very welcome!


Thanks


For the curious, the specific instance I would like to avoid is
reduceBuildVecToShuffle.
It doesn't seem to have any target specific hooks. Exhaustive testing of
x86-64 vector code doesn't show the error. I think the other in tree
targets would notice the vector transform getting the answer wrong (it's
harder to confirm without hardware), so the bug is probably inert for in
tree targets.


Given a v4f16 instance t2, the DAG describes building a v2f16 vector from
elements [0, 2]. The combine translates this to building a vector from
elements [0, 0]. The problem seems to be treating extract_subvector with
different constants as instances of the same value.


t14: v2f16 = extract_subvector t2, Constant:i32<2>

t15: f16 = extract_vector_elt t14, Constant:i32<0>

t16: v2f16 = extract_subvector t2, Constant:i32<0>

t17: f16 = extract_vector_elt t16, Constant:i32<0>


t9: v2f16 = BUILD_VECTOR t17, t15


 ... into: t19: v2f16 = vector_shuffle<0,0> t16, undef:v2f16 // fail
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