[llvm-dev] A9 Scheduler

[Pedro Lopes via llvm-dev]

Hi,

I am having some trouble understanding the scheduling scheme for the C-A9.

Looking at the ARMScheduleA9.td file I find this line that overrides the
target SchedWrite with processor specific latencies.

def : SchedAlias<WriteALU, A9WriteALU>;

However, in this same file, I find the lines presented below, which are
mapping the SchedReadWrite to, for example, the ANDri instruction.

//
===---------------------------------------------------------------------===//
// Subtarget-specific overrides. Map opcodes to list of SchedReadWrite
types.
//
def : InstRW< [WriteALU],
      (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr",
"EORrr",
                 "BICrr")>;


This same instruction is defined in the ARMInstrInfo.td as inheriting from
AsI1_bin_irs (shown below) which, in turn, associates Sched<[WriteALU,
ReadALU]> with the instruction.

defm AND   : AsI1_bin_irs<0b0000, "and",
                          IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>;

In my mind, we have latencies defined from the ProcessorItineraries,
latencies defined in the SchedReadWrite representation which are mapped
through SchedAlias to the ANDri and, in the end, a mapping (or overriding?)
of the latencies in the Itineraries by the processor-specific SchedWrites,
through the InstRW?

Can someone share some light on what scheduling/lantecy information is
being used in this case? I cannot get my head around this... What am I
missing here?

Note: I also do not understand why use instregex if we could use the IIC_*
for the InstRW.

Thanks.

- Tiago
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