[llvm-dev] LLVM back end for the research Connex SIMD processor

[Alex Susu via llvm-dev]

   Hello.
     I'd like to advertise the LLVM back end I developed in the last 2 years for the 
research Connex wide SIMD processor, which can have up to 4096 lanes. The Connex SIMD 
processor is designed to run efficiently BLAS routins, is an easily reconfigurable 
low-power processor with scratchpad memory, a shift register for inter-lane communication, 
a hardware sum-reduction tree and predictable performance - you can find details about it 
at this address: http://users.dcae.pub.ro/~gstefan/2ndLevel/connex.html . The processor 
has a clean design and its Verilog source code could be made open-source.

     You can find the source code of the latest version of the compiler (LLVM back end and 
extensions for Connex in the LoopVectorize module, etc) and runtime I develop for the 
Connex SIMD processor at this address: 
https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_REPO.zip . I would like 
to commit the Connex back end in the very near future in the LLVM repository.
      Also, the Opincaa runtime assembler library contains a great Connex SIMD processor 
simulator, which can be used in case you don't have access to the real processor.

     Please let me know if you are interested in contributing to this work - there are 
plenty of interesting things to be done, closely related to research to compilers and 
high-level synthesis.

     Some papers that describe the compiler and the processor are available at: 
https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_compiler.pdf and 
https://software.intel.com/sites/default/files/managed/d8/cd/catc17-source-to-source-vectorizer-connex-simd-accelerator.pdf 
.
     Please don't hesitate to say if you have any questions or feedback.

   Thank you,
     Alex