[llvm-dev] Question about quad-register

[Anton Korobeynikov via llvm-dev]

The standard trick is to define the "quad register" that would alias
r0/r1/r2/r3. See e.g. ARM backend.

On Sun, Sep 10, 2017 at 6:17 AM, 陳韋任 via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Hi All,
>
>   If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit
> register), is it possible mapping quad-register
> to v4i32 so that the following example work?
>
>     typedef int v4si __attribute__ ((vector_size (16)));
>
>     void foo(v4si i) {
>       v4si j = i;
>     }
>
> I don't know how to write CallingConv.td to represent the concept of
> occupying quad-register R0:R1:R2:R3
> once seeing v4i32. Any example that I can refer to?
>
> Thanks.
>
> Regards,
> chenwj
>
> --
> Wei-Ren Chen (陳韋任)
> Homepage: https://people.cs.nctu.edu.tw/~chenwj
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-- 
With best regards, Anton Korobeynikov
Department of Statistical Modelling, Saint Petersburg State University