[llvm-dev] Meaning of loads/stores marked both atomic and volatile

[Reid Kleckner via llvm-dev]

I would say there are transforms that can be done on atomics that can't be
done on volatile memory ops. For example, llvm should be able to mem2reg
unescaped atomics because it knows they cannot be modified by other
threads, but volatile operations will pin things in memory for use cases
that are mostly outside the abstract model.

On Mon, Nov 20, 2017, 7:26 AM Paweł Batko via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hi llvm-dev,
>
> I read about volatile and atomic modifiers in the docs[1], and I feel
> they make sense to me individually.
> However, I noticed that store[2] and load[3] instructions can be
> marked as both volatile and atomic.
>
> What's the use case for using both volatile and atomic on an
> instruction? Isn't it the case that atomic implies volatile? I guess
> it isn't, but I don't understand why.
>
> I'm guessing that while both volatile and atomic restrict reorderings,
> volatile prevents any kind of load or store elimination optimizations
> but atomic doesn't have such guarantee.
> E.g. I suspect that an atomic load, which can be implemented as a pair
> of a plain load and a fence instruction, can be optimized away to only
> a fence instruction. If it was both volatile and atomic, then such
> optimization would've been illegal.
> In other words, probably very imprecisely, volatile tells the compiler
> what it cannot do while atomic tells the cpu what it should do to
> guarantee certain memory model (and it'd also imply extra constraints
> on what a compiler can do).
>
> My other guess is that it's only to order 'atomic' instruction with
> 'volatile' instruction, thus the former becomes 'atomic volatile'.
>
> I'd appreciate links to any resources on the topic.
>
>
> [1] https://llvm.org/docs/LangRef.html#volatile-memory-accesses
> [2] https://llvm.org/docs/LangRef.html#store-instruction
> [3] https://llvm.org/docs/LangRef.html#i-load
>
> --
> Paweł Batko
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