[llvm-dev] Publication Request: The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend

[Connor Goldberg (RIT Student) via llvm-dev]

Hey everyone,

I would like to add my graduate paper to the list of LLVM publications:
http://scholarworks.rit.edu/theses/9550/

Here's the abstract if anyone is interested:

*The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend*

Compiler infrastructures are often an area of high interest for research.
> As the necessity for digital information and technology increases, so does
> the need for an increase in the performance of digital hardware. The main
> component in most complex digital systems is the central processing unit
> (CPU). Compilers are responsible for translating code written in a
> high-level programming language to a sequence of instructions that is then
> executed by the CPU. Most research in compiler technologies is focused on
> the design and optimization of the code written by the programmer; however,
> at some point in this process the code must be converted to instructions
> specific to the CPU. This paper presents the design of a simplified CPU
> architecture as well as the less understood side of compilers: the backend,
> which is responsible for the CPU instruction generation. The CPU design is
> a 32-bit reduced instruction set computer (RISC) and is written in Verilog.
> Unlike most embedded-style RISC architectures, which have a compiler port
> for GCC (The GNU Compiler Collection), this compiler backend was written
> for the LLVM compiler infrastructure project. Code generated from the LLVM
> backend is successfully simulated on the custom CPU with Cadence Incisive,
> and the CPU is synthesized using Synopsys Design Compiler.


Regards,
Connor
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