[llvm-dev] Some questions about software pipeline in LLVM 4.0.0

[Brendon Cahoon via llvm-dev]

Hi - I replied to the original sender only by mistake. Sorry about that.

 

When we started working on the pipeliner, and added it before the scheduler,
we also were concerned that the scheduler or other passes would undo the
work of the pipeliner. The initial thought was that we would add information
(using metadata or some other way like you've suggested) to the basic block
to tell the scheduler not to schedule the block.  It turns out, that for us,
we never needed to do so.  It was pretty rare that the scheduler would
"undo" the work of the pipeliner. Actually, in the cases that it did, it
turned out to be a problem with the scheduler since it wasn't making good
decisions.

 

In general, most of the extra copies that are added by prior to the register
allocator are eliminated.  Certainly, there are some real copies that end up
being generated, but I think it's better to exclude the copies from the
schedule since most will be eliminated.  Otherwise, including the copies in
the schedule will require resources that may never be used, which is worse
in my opinion.

 

We decided to run the pipeliner on SSA form since the presence of the Phis
helps identify recurrences and other dependences.  Without the Phis, we need
another way to identify recurrences.  Also, if it's done just prior to
register allocation we need to re-generate the liveness information for all
the new virtual registers and CFG. Unfortunately, you're correct - there is
a lot of code that deals with Phis. The code that generates the Phis in the
swp kernel and epilogs is a mess and very complicated.  This portion of the
pipeliner really needs some attention to reduce the complexity and improve
readability.  This has been on my list for quite a while.

 

While I think we could move the location of the pipeliner, I don't think the
extra work to do so would provide much benefit. In general, we've been able
to work around the cases when extra copies or instructions are added, or
when the scheduler messes up the kernel.  Also, for Hexagon, there are many
passes that run after the register that deal with scheduling. If you have
specific cases where you're seeing a problem, it would be interesting to
take a look at them.

 

Thanks,

Brendon

 

From: zhangqiang (CO) [mailto:zhangqiang75 at huawei.com] 
Sent: Thursday, May 25, 2017 3:33 AM
To: llvm-dev at lists.llvm.org
Cc: bcahoon at codeaurora.org
Subject: Some questions about software pipeline in LLVM 4.0.0

 

Hi,

 

I have some questions about the implementation of Software pipeline in
MachinePipeliner.cpp.

 

First, in hexagon backend, between MachinePipeliner and regalloc pass,
there're some other passes like phi eliminate, two-address, register
coalescing, which may change or insert intructions like 'copy' in MBB, and
swp kernel loop may be destroyed by these passes. 

Why not put MachinePipeliner just before reg alloc pass like gcc's modulo
scheduler does? In order to keep SSA pattern? 

I found many codes to process PHI nodes in MachinePipeliner.cpp. So I think
if we move MachinePipeliner just before regalloc, it will simplify the
data/resource dependency graph for SMS.

 

Another question, in gcc, there's a flag BB_DISABLE_SCHEDULE in Basic block,
which is used by SMS to prevent other schedulers from messing with the loop
schedule. So, in llvm , where can I find the similar flag to prevent the
machine scheduler touch the kernel loop?

I have debug some swp cases(hexagon), and find machine scheduler will
re-schedule the SMS kernel loop. Why not add such a flag?

 

 

Best Regards,

 

Thanks

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170531/6e00fca0/attachment-0001.html>