[llvm-dev] Request for comments on optimizing assembler

[Quentin Colombet via llvm-dev]

Hi Colin,

I am definitely interested!

The way I was seeing this happening is by changing incrementally the parser of the MIR format. Basically, I’d like the parser to get smarter and smarter to a point where it could understand assembly mnemonics and build the MachineFunction. The rest of the infrastructure would stay the same.
For different reasons, Matthias already improved the parser to avoid specifying easily computable information. The idea is to continue in that direction.

My 2-c.

Cheers,
-Quentin

> On May 24, 2017, at 12:01 PM, Colin LeMahieu via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hi everyone, we’ve been prototyping an optimizing assembler for Hexagon for the purpose of updating legacy assembly for new architectures, packet rules, and instruction latencies.  It seems like others would be interested in using this and we’re looking for any related feedback: has it been attempted before, who’s interested, or any general suggestions. 
>  
> We’re using the MachineFunctionInitializer created to support MIR in order to process the MC and construct MachineFunctions.
>  
> Currently the workflow sketch is:
> -        Use flags and code from llvm-mc to assemble a file in to an MC representation.
> -        Use a target-specific MachineFunctionInitializer to convert the MC -> MI and write out the contents to a MachineFunction.  
> -        Use flags and code from llc to run the MI through compiler passes for reemission.
>  
> We’d need to either attach it to an existing tool or create a new one and pick somewhere in the pass pipeline to start running passes. 
>  
>  
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