[llvm-dev] Pseudo-instruction that overwrites its input register

[Dr. ERDI Gergo via llvm-dev]

Hi,

I'd like to define a pseudo-instruction whose expansion will, as a 
side-effect, overwrite an input register's value: the pseudo-instruction

ldw r1:r2, P

to load 2 bytes from memory address P is to be expaneded to

ld r1, P+
ld r2, P

where "ld _, P+" is an instruction that loads a single byte from P, and 
post-increments P by one.

How can I represent this behaviour in LLVM? Currently, I have

   let Constraints = "@earlyclobber $reg" in
   def LDWRdPtr : Pseudo<(outs DREGS:$reg),
                         (ins PTRREGS:$ptrreg),
                         "ldw\t$reg, $ptrreg",
                         [(set i16:$reg, (load i16:$ptrreg))]>,
                  Requires<[HasSRAM]>;

The problem, of course, is that with this definition I end up with code 
which assumes it is equivalent to save P before 'ldw r1:r2,P' or after. I 
tried adding "@earlyclobber $ptrreg" as a Constraint, but that just leads 
to an assertion failure during codegen (I assume because @earlyclobber is 
for output ports)

void llvm::MachineOperand::setIsEarlyClobber(bool): Assertion `isReg() && IsDef && "Wrong MachineOperand accessor"' failed.


Thanks,
 	Gergo