[llvm-dev] Some questions about software pipeline in LLVM 4.0.0

[zhangqiang (CO) via llvm-dev]

Hi,

I have some questions about the implementation of Software pipeline in MachinePipeliner.cpp.

First, in hexagon backend, between MachinePipeliner and regalloc pass, there're some other passes like phi eliminate, two-address, register coalescing, which may change or insert intructions like 'copy' in MBB, and swp kernel loop may be destroyed by these passes.
Why not put MachinePipeliner just before reg alloc pass like gcc's modulo scheduler does? In order to keep SSA pattern?
I found many codes to process PHI nodes in MachinePipeliner.cpp. So I think if we move MachinePipeliner just before regalloc, it will simplify the data/resource dependency graph for SMS.

Another question, in gcc, there's a flag BB_DISABLE_SCHEDULE in Basic block, which is used by SMS to prevent other schedulers from messing with the loop schedule. So, in llvm , where can I find the similar flag to prevent the machine scheduler touch the kernel loop?
I have debug some swp cases(hexagon), and find machine scheduler will re-schedule the SMS kernel loop. Why not add such a flag?


Best Regards,

Thanks
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