[llvm-dev] Disabling DAGCombine's specific optimization

[vivek pandya via llvm-dev]

Hello LLVM Developers,

I am working on an architecture which have one bit shift operation if
barrel shiftier hardware is not present in such cases some DAGCombine
optimizations reduces performance of certain benchmarks upto 5% for example
consider follwing optimization:
fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
Here it introduce 2 shift operations and when barrel shiftier is not
present these shifts will be converted to loops thus making it worst. I am
sure there few architectures which have similar features. So how to disable
these kind of optimizations in DAGCombine particularly when I want build
and use LLVM for more than one target ?

Sincerely,
Vivek
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170515/046f5ff3/attachment.html>