[llvm-dev] Bug in TableGen RegisterBankEmitter

[Tom Stellard via llvm-dev]

Hi,

I've run into an issue with the RegisterBankEmitter on the AMDGPU backend.
AMDGPU has a register class: VS_32, which is non-allocatable and contains
registers from both defined register banks (SGPRRegBank and VGPRRegBank).

The RegisterBankEmitter is adding this class to the CoverageData array
for both register classes, because it contains sub-registers of one
of the classes explicitly added to the RegisterBank, for example:

Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64)

This is a problem, because both RegisterBanks think they cover
VS_32, even though neither of them actually do.

What exactly is the best way to fix this?  It seems like we need some
additional checks in the RegisterBankEmitter to fix this, but it's not
clear to me what we should be checking for.

Thanks,
Tom