[llvm-dev] TableGen support for Intrinsics with multiple outputs

[sunwenbo (A) via llvm-dev]

Hi folks,

I am developing backend for a new architecture, which has many Intrinsics with multiple outputs. However, I found TableGen doesn't support such Intrinsics during Instruction Selection.
For example, load intrinsic with address updated.
def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>;

NVPTX has the same situation in the trunk, but it handles all intrinsics in source code which introduced a huge chunk of repetitive codes.

I have a patch for this issue, which is waiting for review.  https://reviews.llvm.org/D32888

Any suggestions are highly appreciated.

Thanks,
Wenbo

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