[llvm-dev] Is there a way to know the target's L1 data cache line size?

[David Abdurachmanov via llvm-dev]

Cavium ThunderX has 128 bytes cache lines.

david

> On 11 Mar 2017, at 13:38, Bruce Hoult via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> ARM can be 32 or 64.


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