[llvm-dev] Is there a way to know the target's L1 data cache line size?

[Hadrien G. via llvm-dev]

Hi everyone,

I'm hailing from the Rust community, where there is a discussion about 
adding facilities for aligning data on an L1 cache line boundary. One 
example of situation where this is useful is when building thread 
synchronization primitives, where avoiding false sharing can be a 
critical concern.

Now, when it comes to implementation, I have this gut feeling that we 
probably do not need to hardcode every target's cache line size in rustc 
ourselves, because there is probably a way to get this information 
directly from the LLVM toolchain that we are using. Is my gut right on 
this one? And can you provide us with some details on how it should be done?

Thanks in advance,
Hadrien