[llvm-dev] Why ISel Shifts operations can only be expanded for Value type vector ?

[vivek pandya via llvm-dev]

Yes I have custom hook for both mul and shifts because if barrel shift
hardware unit is present than we try to optmize MUL to SHL. and if barrel
shiftier is not present than hardware can use MUL and ADD to implement left
shift operation.

- Vivek

On Sat, Mar 4, 2017 at 11:52 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:

> Again to be clear, you r calling a custom hook and not using expand
> correct?
>
> On Mar 4, 2017 10:12 AM, "vivek pandya" <vivekvpandya at gmail.com> wrote:
>
>> Yes that is the file.
>>
>> On Saturday, March 4, 2017, Ryan Taylor <ryta1203 at gmail.com> wrote:
>>
>>> To be clear, where r u trying to lower it? Naturally this should happen
>>> in XXXISelLowering.
>>>
>>> On Mar 4, 2017 8:06 AM, "vivek pandya" <vivekvpandya at gmail.com> wrote:
>>>
>>>>
>>>>
>>>> On Sat, Mar 4, 2017 at 6:26 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>>>>
>>>>> Legalization comes after DAGBuilder.
>>>>>
>>>> I created loop in compiler because I tried to Lower SHL to ISD::MUL
>>>> when I added custom target specific opcode I am able to lower it to mul
>>>> instruction. But then why compiler was going in loop, some code must try to
>>>> convert MUL back to SHL. I will find the reason.
>>>>
>>>> -Vivek
>>>>
>>>>>
>>>>> On Mar 4, 2017 7:39 AM, "vivek pandya" <vivekvpandya at gmail.com> wrote:
>>>>>
>>>>>>
>>>>>>
>>>>>> On Sat, Mar 4, 2017 at 5:57 PM, Ryan Taylor <ryta1203 at gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> Which target independent passes do you mean that are doing this in
>>>>>>> DAG?
>>>>>>>
>>>>>>>
>>>>>>> For example https://github.com/llvm-mirror
>>>>>> /llvm/blob/master/lib/CodeGen/SelectionDAG/SelectionDAGBuild
>>>>>> er.cpp#L3320
>>>>>>
>>>>>> -Vivek
>>>>>>
>>>>>>>
>>>>>>> On Mar 4, 2017 12:22 AM, "vivek pandya" <vivekvpandya at gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On Saturday, March 4, 2017, Ryan Taylor <ryta1203 at gmail.com> wrote:
>>>>>>>>
>>>>>>>>> Why you can't still expand it through MUL with a Custom lowering?
>>>>>>>>> Or am I missing something?
>>>>>>>>>
>>>>>>>>> Yes we can but problem occurs when we know that it is shift with
>>>>>>>> constant value than if we return ISD::MUL with constant imm operand than
>>>>>>>> LLVM will convert it to SHL again because the constant will be power of 2.
>>>>>>>> Thus it creates loop.
>>>>>>>> So we may add target specific ISD node and lower it to mul
>>>>>>>> instruction.
>>>>>>>>
>>>>>>>> --Vivek
>>>>>>>>
>>>>>>>>> Thanks.
>>>>>>>>>
>>>>>>>>> On Fri, Mar 3, 2017 at 12:21 PM, vivek pandya via llvm-dev <
>>>>>>>>> llvm-dev at lists.llvm.org> wrote:
>>>>>>>>>
>>>>>>>>>> Hello LLVM Devs,
>>>>>>>>>>
>>>>>>>>>> I am working on a target on which no SHL instruction is
>>>>>>>>>> available. So wanted to expand it through MUL. But currently it is only
>>>>>>>>>> possible to expand SHL for vector types.
>>>>>>>>>>
>>>>>>>>>> One possible reason I can think is because LLVM tries to optimize
>>>>>>>>>> MUL to SHL in certain cases and that can make compiler co in loop or may
>>>>>>>>>> end up generating wrong code.
>>>>>>>>>>
>>>>>>>>>> But I think SHL should be able to expanded to MUL and to prevent
>>>>>>>>>> looping between MUL and SHL we can put a condition that only optimize MUL
>>>>>>>>>> to SHL when SHL is not expanded operation. The similar logic can be applied
>>>>>>>>>> to DIV and SRA.
>>>>>>>>>>
>>>>>>>>>> If there is any other reasons for not doing this, kindly explain.
>>>>>>>>>>
>>>>>>>>>> Sincerely,
>>>>>>>>>> Vivek
>>>>>>>>>>
>>>>>>>>>> _______________________________________________
>>>>>>>>>> LLVM Developers mailing list
>>>>>>>>>> llvm-dev at lists.llvm.org
>>>>>>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>
>>>>>>
>>>>
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