[llvm-dev] Specifying conditional blocks for the back end

[Friedman, Eli via llvm-dev]

On 3/2/2017 7:07 PM, Alex Susu via llvm-dev wrote:
>   Hello.
>     For my back end for the Connex SIMD research processor I want to 
> implement conditional blocks (I guess the better term is predicated 
> blocks). Predicated blocks are bordered by two instructions WHEREEQ 
> (or WHERELT, etc) and ENDWHERE.
>     For example, the following code executes the instructions inside 
> the WHERE block only for the lanes where R0 == R1:
>         EQ R0, R1;
>         WHEREEQ
>           vector_asm_instr1;
>           ...
>           vector_asm_instrk;
>         ENDWHERE
>
>     I was able to generate at instruction selection such a block by 
> writing custom C++ selection code, but I don't know how can I inform 
> the back end that the instructions inside the WHERE block get executed 
> conditionally, not always.
>     This matters it seems only for optimization levels in llc -O1/2/3, 
> but not for O0. For levels of optimization O1/2/3, I experienced cases 
> where the WHEREEQ and ENDWHERE instructions were simply removed and 
> the vector_asm_instr1..k became executed unconditionally, etc - and 
> this is NOT good.
>
>     Could you please tell me how can I inform the back end that the 
> instructions inside my WHERE blocks get executed conditionally, not 
> always. 

There's some existing infrastructure in the backend for predication; see 
lib/CodeGen/IfConversion.cpp (and the target hooks PredicateInstruction 
etc.).  For forming blocks, you might want to follow what the ARM 
backend does for Thumb2; see Thumb2ITBlockPass.cpp .

-Eli

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