[llvm-dev] default predicate operands

[Davis, Alan via llvm-dev]

I'm trying to define a register-based predicate operand that will appear in the "ins" list of most MachineInstrs. It will be Initialized with a default value meaning "unconditional" in most cases but instantiated via the pattern in explicitly conditional instructions.

I tried this:

def myPred : OperandWithDefaultOps<
   i64, (ops (i64 zero_reg), (i32 0))> { 
   let MIOperandInfo = (ops (i64 Scalar64:$creg), (i32 i32imm:$cc));  
}

def myInst : Instruction {
  let InOperandList = (ins myPred:$p, Scalar32:$src1, Scalar32:$src2);   
  let OutOperandList = (outs Scalar32:$dst);
  let Pattern = [(set i32:$dst, (add Scalar32:$src1, Scalar32:$src2))];
}

but tablegen faults with some kind of type mismatch.

llvm-tblgen: llvm/include/llvm/Support/Casting.h:237: typename llvm::cast_retty<X, Y*>::ret_type llvm::cast(Y*) [with X = llvm::DefInit; Y = llvm::Init; typename llvm::cast_retty<X, Y*>::ret_type = llvm::DefInit*]: Assertion `isa<X>(Val) && "cast<Ty>() argument of incompatible type!"' failed.

Am I doing something wrong or is this just a bug in tablegen?

-Alan