[llvm-dev] Wide load/store optimization question

[Tom Stellard via llvm-dev]

On 06/13/2017 11:44 AM, Peter Bel via llvm-dev wrote:
> Hi,
> 
> I'm trying to write an LLVM backend for Epiphany arch, and I wonder if someone can give me some advice on how to implement load/store optimization. The CPU itself is 32-bit, but it supports wider 64-bit loads and store. So the basic idea is to make use of those by combining narrow ones.
> 
> I've checked how it is done in AArch64 and Hexagon, and my current code is very close to the AArch64 one (used it as a kick-off). The problem lies in constraints imposed by the platform.
> 
> The main constraint is that regs used should be sequential, lower reg should be even/zero. And obviously frame offsets should be sequential to be merged, dword-aligned for the lower reg offset.
> 
> Because of those constraints I'm currently running this pass on pre-emit, after RA and frame finalization. But at that point most of the choices made (RA, frame offsets), and those are obviously suboptimal. The most common issue can look somehow like this:
>     str r1, [fp, -4]
>     str r2, [fp, -8]
> Those two stores can't be merged because the lower reg (r1) is not even. To merge them, r1 should be changed to r0, and r2 to r1. Sometimes the same problem happens when the frame offset is misaligned, e.g. r0 will have offset aligned to word, not dword.
> 
> Can someone please point me out in which direction should I move? And also - at which step should I apply such pass? If on PreRA - how to set reg constraints such as regsequence, as well as frame constraints? If before frame finalization - how to  set frame constraints? If on pre-emit like i'm doing now - how to optimize and rewrite frame offsets and regs?
> 

One thing you can do is define a register class that is made up of register
tuples e.g. r0r1, r2r3, etc., and use that register class for the 64-bit
load/store instructions.  This will allow you to do the load/store
merging before register allocation without the register constraints.

The AMDGPU backend has similar alignment constraints for its
SGPR classes, where if you are writing to N-consecutive SGPRs,
then the lower register index must be divisible by N.

-Tom

> Thanks,
> Petr
> 
> 
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