[llvm-dev] Clarification: machine operand subreg, <def, read-undef>, and IMPLICIT_DEF

[Johnson, Nicholas Paul via llvm-dev]

Hey,

Suppose I have this MachineInstr:
    %vreg190:sub_32_1<def,read-undef> = IMPLICIT_DEF; PairRegs:%vreg190

(on my backend, the 'PairRegs' register class hold 2-vectors of i32 values)

I want to make sure I understand the combination of subreg and read-undef correctly.  According to the comment in MachineOperand.h, quote:
  /// ...  On a sub-register def operand, it refers to the part of the
  /// register that isn't written. ...

So, am I correct to say that the above instruction is equivalent to the following?
    %vreg190<def> = IMPLICIT_DEF; PairRegs:%vreg190

Or if there is a subtle distinction, please help me understand it. 

Thank you,
Nick Johnson
D. E. Shaw Research