[llvm-dev] Possible llc bug: "Virtual register defs don't dominate all uses."

[Alex Susu via llvm-dev]

   Hello.
     I am experiencing some errors in the back end (which I presume are actually a bug of 
lib/CodeGen/MachineVerifier.cpp) such as:
       *** Bad machine code: Virtual register defs don't dominate all uses. ***
       - function:    MatMul_RowMajor_Transposed
       - v. register: %vreg93

       *** Bad machine code: Virtual register defs don't dominate all uses. ***
       - function:    MatMul_RowMajor_Transposed
       - v. register: %vreg88
       LLVM ERROR: Found 2 machine code errors.

     These errors are given because of the following machine basic block:
       BB#5: derived from LLVM BB %middle.block
         Predecessors according to CFG: BB#4
           %vreg88<def,dead> = LDSH_H
           ; IMPORTANT: here an instruction bundle starts
           %vreg92<def,dead> = EQ_H [...]
             * NOP
             * WHEREEQ
             * %vreg93<def> = VLOAD_H 0
             * %vreg87<def> = ORV_H %vreg86, %vreg93
             * %vreg89<def> = ORV_H %vreg88, %vreg93
           ; IMPORTANT: here the instruction bundle ends
           ENDWHERE
           RED_H %vreg87
           RED_H %vreg89

     Basically the problem is related to the fact I have created an instruction bundle in 
which I define and use virtual register %vreg93 and also I use %vreg88 defined above it 
(note that if I do NOT use inside the bundle a virtual register I do not get this error).

     Did anybody else encounter something like this? It looks to me this is actually a bug 
of lib/CodeGen/MachineVerifier.cpp. Can you tell me how can I address this problem?

   Thank you,
     Alex