[llvm-dev] Pseudo-instruction that overwrites its input register
Dr. ERDI Gergo via llvm-dev
llvm-dev at lists.llvm.org
Sun Jun 4 00:04:32 PDT 2017
On Sun, 4 Jun 2017, Dr. ERDI Gergo wrote:
> the type difference I mentioned ((i16, i16, ch) vs (i16, ch) on the
> output ports)
OK I managed to make some progress on this, by using a MergeValues node:
SDNode* LDW = CurDAG->getMachineNode(
AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other,
LD->getBasePtr(), LD->getChain());
SDValue Unpack[] = { SDValue(LDW, 0), SDValue(LDW, 2) };
SDNode* NN = CurDAG->getMergeValues(Unpack, SDLoc(N)).getNode();
ReplaceNode(N, NN);
which gets me from
t17: i16,ch = load<LD2[%v25](align=1)(dereferenceable)> t16:1, t2, undef:i16
to
t24: i16,i16,ch = LDWRdPtr t2, t16:1
looking tood; but then it fails during scheduling with
llc: CodeGen/SelectionDAG/InstrEmitter.cpp:303:
unsigned int llvm::InstrEmitter::getVR(
llvm::SDValue,
llvm::DenseMap<llvm::SDValue, unsigned int>&):
Assertion `I != VRBaseMap.end() && "Node emitted out of order - late"' failed.
For reference, the full DAG before and after ISEL:
SelectionDAG has 22 nodes:
t0: ch = EntryToken
t2: i16,ch = CopyFromReg t0, Register:i16 %vreg0
t5: i16,ch = load<LD2[%v25](align=1)(dereferenceable)> t0, t2, undef:i16
t9: ch,glue = callseq_start t5:1, TargetConstant:i16<0>
t11: ch,glue = CopyToReg t9, Register:i16 %R25R24, t5
t13: ch,glue = CALL t11, TargetGlobalAddress:i16<i8 (i16)* @read_ram> 0, Register:i16 %R25R24, RegisterMask:Untyped, t11:1
t14: ch,glue = callseq_end t13, TargetConstant:i16<0>, TargetConstant:i16<0>, t13:1
t16: i8,ch,glue = CopyFromReg t14, Register:i8 %R24, t14:1
t17: i16,ch = load<LD2[%v25](align=1)(dereferenceable)> t16:1, t2, undef:i16
t18: ch,glue = callseq_start t17:1, TargetConstant:i16<0>
t19: ch,glue = CopyToReg t18, Register:i16 %R25R24, t17
t20: ch,glue = CALL t19, TargetGlobalAddress:i16<i8 (i16)* @read_ram> 0, Register:i16 %R25R24, RegisterMask:Untyped, t19:1
t21: ch,glue = callseq_end t20, TargetConstant:i16<0>, TargetConstant:i16<0>, t20:1
t22: i8,ch,glue = CopyFromReg t21, Register:i8 %R24, t21:1
t23: ch = RET_FLAG t22:1
SelectionDAG has 23 nodes:
t0: ch = EntryToken
t2: i16,ch = CopyFromReg t0, Register:i16 %vreg0
t9: i16,ch,glue = ADJCALLSTACKDOWN TargetConstant:i16<0>, t27:1
t11: ch,glue = CopyToReg t9:1, Register:i16 %R25R24, t27
t13: ch,glue = CALLk TargetGlobalAddress:i16<i8 (i16)* @read_ram> 0, Register:i16 %R25R24, RegisterMask:Untyped, t11, t11:1
t14: i16,ch,glue = ADJCALLSTACKUP TargetConstant:i16<0>, TargetConstant:i16<0>, t13, t13:1
t18: i16,ch,glue = ADJCALLSTACKDOWN TargetConstant:i16<0>, t25:1
t19: ch,glue = CopyToReg t18:1, Register:i16 %R25R24, t25
t20: ch,glue = CALLk TargetGlobalAddress:i16<i8 (i16)* @read_ram> 0, Register:i16 %R25R24, RegisterMask:Untyped, t19, t19:1
t21: i16,ch,glue = ADJCALLSTACKUP TargetConstant:i16<0>, TargetConstant:i16<0>, t20, t20:1
t16: i8,ch,glue = CopyFromReg t14:1, Register:i8 %R24, t14:2
t24: i16,i16,ch = LDWRdPtr t2, t16:1
t25: i16,ch = merge_values t24, t24:2
t26: i16,i16,ch = LDWRdPtr t2, t0
t27: i16,ch = merge_values t26, t26:2
t22: i8,ch,glue = CopyFromReg t21:1, Register:i8 %R24, t21:2
t23: ch = RET t22:1
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