[llvm-dev] Pseudo-instruction that overwrites its input register

[Dr. ERDI Gergo via llvm-dev]

On Tue, 30 May 2017, Nemanja Ivanovic wrote:

> So the idea is that you specify your `outs` in the instruction definition, one of
> those will have a `RegConstraint` on them and finally, you emit these nodes in your
> <TargetName>ISelDAGToDAG.cpp.

OK, thanks, I now get the basic idea -- but I'm still struggling with the 
implementation.

In my ISelDATToDAG, if I match something like

Selecting: t17: i16,ch = load<LD2[%v25](align=1)(dereferenceable)> t16:1, t2, undef:i16

then whatever I return as the machine node, it will have to be of the same 
type, i.e. (i16, ch), right? But if I have this extra output port for the 
changed address register, that means my output is now (i16, i16, ch). It 
is unclear to me how to reconcile that with the original abstract node 
that I'm matching on.

In more concrete terms, I tried ignoring this and just copying the address 
argument and the chain:

     const LoadSDNode *LD = cast<LoadSDNode>(N);
     int Offs = cast<ConstantSDNode>(LD->getOffset())->getSExtValue();
     if (AM == ISD::UNINDEXED && Offs == 0) {
       SDNode* LDW = CurDAG->getMachineNode(
         AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other,
         LD->getBasePtr(), LD->getChain());

       ReplaceNode(N, LDW);
       return true;
     }

but this fails with

/home/cactus/prog/rust/rust-avr/llvm/include/llvm/Support/Casting.h:222: 
typename std::enable_if<(! llvm::is_simple_type<Y>::value), typename 
llvm::cast_retty<X, const Y>::ret_type>::type llvm::cast(const Y&)
[with X = llvm::ConstantSDNode;
       Y = llvm::SDValue;
       typename std::enable_if<(!llvm::is_simple_type<Y>::value),
       typename llvm::cast_retty<X, const Y>::ret_type>::type = llvm::ConstantSDNode*]:
Assertion `isa<X>(Val) && "cast<Ty>() argument of incompatible type!"' failed.

Any more hints, please?

Thanks,
 	Gergo