[llvm-dev] How to migrate x86_sse2_psrl_dq after LLVM v3.8?
Leslie Zhai via llvm-dev
llvm-dev at lists.llvm.org
Tue Jul 25 20:36:02 PDT 2017
Thanks for your kind response!
在 2017年07月25日 22:30, Craig Topper 写道:
> We should still parse IR containing that intrinsic and turn into
> something equivalent. You can see what that looks like by running it
> through the opt binary without running any passes.
I am migrating dragonegg https://reviews.llvm.org/D35667 I will test it
without running any PASS.
> If you're trying to generate IR and you used to generate that
> intrinsic, you'll need to generate an equivalent shufflevector
> instruction. You can find code for that in AutoUpgrade.cpp
I just grep sse2.psrl.dq in lib/IR/AutoUpgrade.cpp, there is
UpgradeX86PSRLDQIntrinsics for x86.sse2.psrl.dq, and emit a shuffle to
move the bytes if (Shift < 16), else just return the zero vector
so could I migrate dragonegg for the if (ShiftVal < 32) condition like
> On Tue, Jul 25, 2017 at 1:30 AM Leslie Zhai <lesliezhai at llvm.org.cn
> <mailto:lesliezhai at llvm.org.cn>> wrote:
> Hi LLVM developers,
> After Remove int_x86_sse2_psll_dq_bs and int_x86_sse2_psrl_dq_bs
> intrinsics. The builtins aren't used by clang.
> https://reviews.llvm.org/rL229069 there was no
> Intrinsic::x86_sse2_psrl_dq any more, then how to migrate:
> Function *F =
> Result =
> Builder.CreateCall(F, ArrayRef<Value *>(&Ops, 2),
> And clang v3.9 migrated X86::BI__builtin_ia32_palignr128 like this
> just ignored the if (shiftVal < 32) condition?
> Please give me some hint, thanks a lot!
> Leslie Zhai - a LLVM developer https://reviews.llvm.org/p/xiangzhai/
Leslie Zhai - a LLVM developer https://reviews.llvm.org/p/xiangzhai/
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