[llvm-dev] How to lower a 'Store' node using the list<dag> pattern.
Tim Northover via llvm-dev
llvm-dev at lists.llvm.org
Mon Jul 24 07:05:32 PDT 2017
On 24 July 2017 at 03:34, Dominique Torette via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> def MOVSUTO_SU_rr : CLPSUInst_rr<0b1000001100,
> (ins SURegisterOperand:$RegA),
> (outs SURegisterOperand:$RegB),
> [(store (i16 SURegisterOperand:$RegA), i16:$RegB)], NoItinerary>
Store instructions usually just have two "ins" operands (the value to
be stored and the address to store it). Their actual "out" is actually
memory, which LLVM doesn't model at this level.
This is certainly what LLVM's "store" DAG node is expecting to deal
with and could easily cause an assertion failure in tablegen.
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