[llvm-dev] error:Ran out of lanemask bits to represent subregister
hameeza ahmed via llvm-dev
llvm-dev at lists.llvm.org
Fri Jul 14 10:36:31 PDT 2017
The code file is attached here.
Kindly check it.
On Fri, Jul 14, 2017 at 10:29 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> Do your 32768 registers also have sub registers?
>
> I can't tell you exactly what to change. I'm not familiar with the code. I
> would just be running grep or something.
>
> ~Craig
>
> On Fri, Jul 14, 2017 at 10:23 AM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Thank you so much. I think there is no issue with my definitions since i
>> have to use larger registers i.e 65536 bit register made from 2 32768
>> registers.
>> I have seen your mentioned code files. But it looks difficult what to
>> change.
>> Could you please specify exactly where to make changes??
>>
>> Thank You
>>
>> On Fri, Jul 14, 2017 at 10:16 PM, Craig Topper <craig.topper at gmail.com>
>> wrote:
>>
>>> This error indicates that its trying to create a lane mask larger than
>>> 32 bits. Without seeing all of your subregister definitions I can't tell if
>>> that's correct of if there's something wrong with your register definitions.
>>>
>>> If it is correct then you need to change all the associated LaneMask
>>> code in CodeGenRegisters.cpp, include/llvm/MC/LaneBitMask.h and probably
>>> elsewhere to use a larger type than "unsigned" or "uint32_t".
>>>
>>> ~Craig
>>>
>>> On Fri, Jul 14, 2017 at 10:09 AM, Tim Northover <t.p.northover at gmail.com
>>> > wrote:
>>>
>>>> Your first post was 6 hours ago and you've pinged it twice. That's too
>>>> frequent, the generally accepted ping rate on llvm lists is once per week.
>>>>
>>>> Tim.
>>>>
>>>> On Jul 14, 2017 1:07 PM, "hameeza ahmed via llvm-dev" <
>>>> llvm-dev at lists.llvm.org> wrote:
>>>>
>>>>> please tell me how to solve this lanemask bits issue?
>>>>>
>>>>> how to increase lanemask bits?
>>>>>
>>>>> On Fri, Jul 14, 2017 at 8:33 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>>>> wrote:
>>>>>
>>>>>>
>>>>>> Hello,
>>>>>> i am trying to construct a register of size 65536 bit by combining 2
>>>>>> registers of 32768 bits. both the 32768 bit registers are different so i
>>>>>> have to use the following method
>>>>>>
>>>>>> let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs
>>>>>> = 1 in
>>>>>>
>>>>>> but i am getting following error..
>>>>>>
>>>>>> error:Ran out of lanemask bits to represent subregister
>>>>>> sub_32768bit_hi_then_sub_16384bit_hi_then_sub_32bit
>>>>>>
>>>>>> now how to increase lanemask bits? what changes are required
>>>>>> in IntrinsicEmitter.cpp file??
>>>>>>
>>>>>> Please reply.
>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> LLVM Developers mailing list
>>>>> llvm-dev at lists.llvm.org
>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>>
>>>>>
>>>
>>
>
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let Namespace = "R" in {
def sub_32bit : SubRegIndex<32>;
def sub_64bit : SubRegIndex<64>;
def sub_128bit : SubRegIndex<128>;
def sub_256bit : SubRegIndex<256>;
def sub_512bit : SubRegIndex<512>;
def sub_1024bit : SubRegIndex<1024>;
def sub_2048bit : SubRegIndex<2048>;
def sub_2048bit_hi : SubRegIndex<2048, 2048>;
def sub_4096bit : SubRegIndex<4096>;
def sub_4096bit_hi : SubRegIndex<4096, 4096>;
def sub_8192bit : SubRegIndex<8192>;
def sub_8192bit_hi : SubRegIndex<8192, 8192>;
def sub_16384bit : SubRegIndex<16384>;
def sub_16384bit_hi : SubRegIndex<16384, 16384>;
def sub_32768bit : SubRegIndex<32768>;
def sub_32768bit_hi : SubRegIndex<32768, 32768>;
}
foreach J = 0-31 in {
foreach I = 0-511 in
{
def R_#J#_REG32b_#I : R_CLASS<"R_" #J# "R32b_"#I, I>, DwarfRegNum<[I]>; }
let SubRegIndices = [sub_32bit] in {
foreach I = 0-255 in
def R_#J#_REG64b_#I : R_CLASS<"R_"#J#"_R64b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG32b_"#I)]>;
}
let SubRegIndices = [sub_64bit] in {
foreach I = 0-127 in
def R_#J#_REG128b_#I : R_CLASS<"R_"#J#"_R128b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG64b_"#I)]>;
}
let SubRegIndices = [sub_128bit] in {
foreach I = 0-63 in
def R_#J#_REG256b_#I : R_CLASS<"R_"#J#"_R256b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG128b_"#I)]>;
}
let SubRegIndices = [sub_256bit] in {
foreach I = 0-31 in
def R_#J#_REG512b_#I : R_CLASS<"R_"#J#"_R512b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG256b_"#I)]>;
}
let SubRegIndices = [sub_512bit], CoveredBySubRegs = 1 in {
foreach I = 0-15 in
def R_#J#_REG1024b_#I : R_CLASS<"R_"#J#"_R1024b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG512b_"#I)]>;
}
let SubRegIndices = [sub_1024bit] in {
foreach I = 0-7 in
def R_#J#_REG2048b_#I : R_CLASS<"R_"#J#"_R2048b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG1024b_"#I)]>;
}
} //end of J loop
let SubRegIndices = [sub_2048bit, sub_2048bit_hi], CoveredBySubRegs = 1 in {
foreach I = 0-7 in
{ def R_0_1_REG4Kb_#I : R_CLASS<"R_0_1_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_REG2048b_"#I), !cast<R_CLASS>("R_1_REG2048b_"#I)]>;
def R_2_3_REG4Kb_#I : R_CLASS<"R_2_3_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_2_REG2048b_"#I), !cast<R_CLASS>("R_3_REG2048b_"#I)]>;
def R_4_5_REG4Kb_#I : R_CLASS<"R_4_5_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_4_REG2048b_"#I), !cast<R_CLASS>("R_5_REG2048b_"#I)]>;
def R_6_7_REG4Kb_#I : R_CLASS<"R_6_7_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_6_REG2048b_"#I), !cast<R_CLASS>("R_7_REG2048b_"#I)]>;
def R_8_9_REG4Kb_#I : R_CLASS<"R_8_9_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_8_REG2048b_"#I), !cast<R_CLASS>("R_9_REG2048b_"#I)]>;
def R_10_11_REG4Kb_#I : R_CLASS<"R_10_11_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_10_REG2048b_"#I), !cast<R_CLASS>("R_11_REG2048b_"#I)]>;
def R_12_13_REG4Kb_#I : R_CLASS<"R_12_13_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_12_REG2048b_"#I), !cast<R_CLASS>("R_13_REG2048b_"#I)]>;
def R_14_15_REG4Kb_#I : R_CLASS<"R_14_15_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_14_REG2048b_"#I), !cast<R_CLASS>("R_15_REG2048b_"#I)]>;
def R_16_17_REG4Kb_#I : R_CLASS<"R_16_17_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_REG2048b_"#I), !cast<R_CLASS>("R_17_REG2048b_"#I)]>;
def R_18_19_REG4Kb_#I : R_CLASS<"R_18_19_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_18_REG2048b_"#I), !cast<R_CLASS>("R_19_REG2048b_"#I)]>;
def R_20_21_REG4Kb_#I : R_CLASS<"R_20_21_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_20_REG2048b_"#I), !cast<R_CLASS>("R_21_REG2048b_"#I)]>;
def R_22_23_REG4Kb_#I : R_CLASS<"R_22_23_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_22_REG2048b_"#I), !cast<R_CLASS>("R_23_REG2048b_"#I)]>;
def R_24_25_REG4Kb_#I : R_CLASS<"R_24_25_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_24_REG2048b_"#I), !cast<R_CLASS>("R_25_REG2048b_"#I)]>;
def R_26_27_REG4Kb_#I : R_CLASS<"R_26_27_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_26_REG2048b_"#I), !cast<R_CLASS>("R_27_REG2048b_"#I)]>;
def R_28_29_REG4Kb_#I : R_CLASS<"R_28_29_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_28_REG2048b_"#I), !cast<R_CLASS>("R_29_REG2048b_"#I)]>;
def R_30_31_REG4Kb_#I : R_CLASS<"R_30_31_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_30_REG2048b_"#I), !cast<R_CLASS>("R_31_REG2048b_"#I)]>;
}
}
let SubRegIndices = [sub_4096bit, sub_4096bit_hi], CoveredBySubRegs = 1 in {
foreach I = 0-7 in
{ def R_0_1_2_3_REG8Kb_#I : R_CLASS<"R_0_1_2_3_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_REG4Kb_"#I), !cast<R_CLASS>("R_2_3_REG4Kb_"#I)]>;
def R_4_5_6_7_REG8Kb_#I : R_CLASS<"R_4_5_6_7_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_4_5_REG4Kb_"#I), !cast<R_CLASS>("R_6_7_REG4Kb_"#I)]>;
def R_8_9_10_11_REG8Kb_#I : R_CLASS<"R_8_9_10_11_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_8_9_REG4Kb_"#I), !cast<R_CLASS>("R_10_11_REG4Kb_"#I)]>;
def R_12_13_14_15_REG8Kb_#I : R_CLASS<"R_12_13_14_15_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_12_13_REG4Kb_"#I), !cast<R_CLASS>("R_14_15_REG4Kb_"#I)]>;
def R_16_17_18_19_REG8Kb_#I : R_CLASS<"R_16_17_18_19_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_17_REG4Kb_"#I), !cast<R_CLASS>("R_18_19_REG4Kb_"#I)]>;
def R_20_21_22_23_REG8Kb_#I : R_CLASS<"R_20_21_22_23_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_20_21_REG4Kb_"#I), !cast<R_CLASS>("R_22_23_REG4Kb_"#I)]>;
def R_24_25_26_27_REG8Kb_#I : R_CLASS<"R_24_25_26_27_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_24_25_REG4Kb_"#I), !cast<R_CLASS>("R_26_27_REG4Kb_"#I)]>;
def R_28_29_30_31_REG8Kb_#I : R_CLASS<"R_28_29_30_31_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_28_29_REG4Kb_"#I), !cast<R_CLASS>("R_30_31_REG4Kb_"#I)]>;
}
}
let SubRegIndices = [sub_8192bit, sub_8192bit_hi], CoveredBySubRegs = 1 in {
foreach I = 0-7 in
{ def R_0_1_2_3_4_5_6_7_REG16Kb_#I : R_CLASS<"R_0_1_2_3_4_5_6_7_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_2_3_REG8Kb_"#I), !cast<R_CLASS>("R_4_5_6_7_REG8Kb_"#I)]>;
def R_8_9_10_11_12_13_14_15_REG16Kb_#I : R_CLASS<"R_8_9_10_11_12_13_14_15_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_8_9_10_11_REG8Kb_"#I), !cast<R_CLASS>("R_12_13_14_15_REG8Kb_"#I)]>;
def R_16_17_18_19_20_21_22_23_REG16Kb_#I : R_CLASS<"R_16_17_18_19_20_21_22_23_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_17_18_19_REG8Kb_"#I), !cast<R_CLASS>("R_20_21_22_23_REG8Kb_"#I)]>;
def R_24_25_26_27_28_29_30_31_REG16Kb_#I : R_CLASS<"R_24_25_26_27_28_29_30_31_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_24_25_26_27_REG8Kb_"#I), !cast<R_CLASS>("R_28_29_30_31_REG8Kb_"#I)]>;
}
}
let SubRegIndices = [sub_16384bit, sub_16384bit_hi], CoveredBySubRegs = 1 in {
foreach I = 0-7 in
{ def R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_REG32Kb_#I : R_CLASS<"R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_R32Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_2_3_4_5_6_7_REG16Kb_"#I), !cast<R_CLASS>("R_8_9_10_11_12_13_14_15_REG16Kb_"#I)]>;
def R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG32Kb_#I : R_CLASS<"R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_R32Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_17_18_19_20_21_22_23_REG16Kb_"#I), !cast<R_CLASS>("R_24_25_26_27_28_29_30_31_REG16Kb_"#I)]>;
}
}
let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = 1 in {
foreach I = 0-7 in
def R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG64Kb_#I : R_CLASS<"R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_R64Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_REG32Kb_"#I), !cast<R_CLASS>("R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG32Kb_"#I)]>;
}
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