[llvm-dev] Using new types v32f32, v32f64 in llvm backend not possible

[hameeza ahmed via llvm-dev]

Thank you so much. it run fine.
Can you please resolve  following issue;

I now have support for v2048i32
but my backend supports v64i32
so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the
only difference between 2 is if its orginally v2048i32 i want my registers
assignment from REG_A set. if its v64i32 originally, then i want registers
from set REG_B.


How to accomplish this???

I am really stuck at this point.

Please guide me.

Thank You


On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote:

>
> On 07/11/2017 03:22 AM, hameeza ahmed wrote:
>
>> Hello,
>>
>> i want to work with these types v32f32, v32f64.... in llvm which are
>> undefined in the backend?
>> But v32i32, v32i64 are already defined so i am able to use these.
>>
>> but for other types such as v32f32, v32f64 although i have defined them
>> appropriately in all the files like machinevaluetype.h,  valuetypes.cpp
>> etc. i have checked it many times but still getting the following error
>> when build in debug mode.
>>
>> llvm-tblgen: /utils/TableGen/CodeGenDAGPatterns.cpp:57:
>> llvm::EEVT::TypeSet::TypeSet(MVT::SimpleValueType, llvm::TreePattern &):
>> Assertion `(VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR || VT ==
>> MVT::iPTRAny || VT == MVT::Any) && "Not a concrete type!"' failed.
>>
>
> Are you sure that you updated all of the enum values correctly, including
> updating MVT::LAST_VALUETYPE, etc., and also updated
> utils/TableGen/CodeGenTarget.cpp?
>
>  -Hal
>
>
>
>>
>> What could be the reason?? please guide how to define new types in llvm
>> backend.
>>
>>
>> Thank You
>>
>
> --
> Hal Finkel
> Lead, Compiler Technology and Programming Languages
> Leadership Computing Facility
> Argonne National Laboratory
>
>
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