[llvm-dev] Error in v64i32 type in x86 backend

[hameeza ahmed via llvm-dev]

Thank You. well i have seen these links. but they dont cover the problem
that i have mentioned. actually i am doing all the things step by step.

so i havent yet worked with instruction selection phase/ files. rather
before that i am trying to do legalization by allowing vector elements>16
i.e 64xi32. here i have mainly worked with 2 files uptil now, i.e
registerinfo.td to define register class to be called in legalization. and
most importantly i am dealing with file X86ISelLowering.cpp.

Now is there any relation in this and instruction selection. since
instruction selection comes after combine and legalize so i havent yet
worked on it.


Please correct me, I am stuck here.

Thank You again

On Fri, Jul 7, 2017 at 7:11 AM, Friedman, Eli <efriedma at codeaurora.org>
wrote:

> Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and
> http://llvm.org/docs/CodeGenerator.html ?  http://llvm.org/docs/
> WritingAnLLVMBackend.html#instruction-selector describes how to define a
> store instruction.
>
> -Eli
>
>
> On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote:
>
> Please correct me i m stuck at this point.
>
> On Jul 6, 2017 5:18 PM, "hameeza ahmed" <hahmed2305 at gmail.com> wrote:
>
> Hello,
> i am experimenting with the increase in register/ vector width to 64
> elements of 32 bits instead of 16 in x86 backend.
> for eg.
> i have a loop with 65 iterations;
> if my IR generates v64i32 and 1 scalar, still the backend breaks the
> v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128
> elements in loop then it should break it into 2 v64i32 instructions.
>
> in order to do this i have made necessary changes in X86ISelLowering.cpp.
> and rebuild llvm. then when i use the command -view-dag-combine2-dags i
> get the required output in graph but the following error on console:
>
> LLVM ERROR: Cannot select: t10: ch = store<ST256[bitcast ([65 x i32]* @a
> to <64 x i32>*)](align=16)(tbaa=<0x30c5438>)> t9, t7, t12, undef:i64
>   t7: v64i32 = add t6, t4
>     t6: v64i32,ch = load<LD256[bitcast ([65 x i32]* @c to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t14, undef:i64
>       t14: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @c> 0
>         t13: i64 = TargetGlobalAddress<[65 x i32]* @c> 0
>       t3: i64 = undef
>     t4: v64i32,ch = load<LD256[bitcast ([65 x i32]* @b to <64 x
> i32>*)](align=16)(tbaa=<0x30c5438>)(dereferenceable)> t0, t16, undef:i64
>       t16: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @b> 0
>         t15: i64 = TargetGlobalAddress<[65 x i32]* @b> 0
>       t3: i64 = undef
>   t12: i64 = X86ISD::Wrapper TargetGlobalAddress:i64<[65 x i32]* @a> 0
>     t11: i64 = TargetGlobalAddress<[65 x i32]* @a> 0
>   t3: i64 = undef
> In function: foo
>
> The dag after legalization is also attached here.
>
> the source is vector sum of 65 elements.
>
>
> Kindly correct me.
>
>
>
>
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