[llvm-dev] registers and sub registers - duplicate keys to match on

[Edoardo Fusella via llvm-dev]

Hello
I'm dealing with an implementation from scratch of a backend. However,
although I reached some first good results, now I'm facing a quite strange
issue that I'm not able to figure out.

In my Arch0RegisterInfo.td, I have:

def sub_even : SubRegIndex<32>;
def sub_odd  : SubRegIndex<32, 32>;

class Arch0GPRReg<bits<16> Enc, string n> : Arch0Reg<Enc, n>;
class Arch064GPRReg<bits<16> Enc, string n, list<Register> subregs>
  : Arch0RegWithSubRegs<Enc, n, subregs> {
  let SubRegIndices = [sub_even, sub_odd];
  let CoveredBySubRegs = 1;
}

and then:

foreach i = 0-57 in {
    def S#i : Arch0GPRReg<i, "s"#i>, DwarfRegNum<[i]>;
}
foreach i = 0-28 in {
  def S#!shl(i, 1)#_S#!add(!shl(i, 1), 1) : Arch064GPRReg<!shl(i, 1),
"s"#!shl(i, 1),
               [!cast<Arch0GPRReg>("S"#!shl(i, 1)),
                !cast<Arch0GPRReg>("S"#!add(!shl(i, 1), 1))]>;
}

The two loops will generate something like this:
def S0 : Arch0GPRReg<0, "s0">, DwarfRegNum<[0]>;
def S1 : Arch0GPRReg<1, "s1">, DwarfRegNum<[1]>;
def S2 : Arch0GPRReg<2, "s2">, DwarfRegNum<[2]>;
def S3 : Arch0GPRReg<3, "s3">, DwarfRegNum<[3]>;
...

def S0_S1 : Arch064GPRReg<0, "s0", [S0, S1]>;
def S2_S3 : Arch064GPRReg<2, "s2", [S2, S3]>;
...


I would like to have 32 bit general purpose registers that could be taken
in pairs to have 64 bit registers.

However, when I compile in debug mode, I got the following error message:
Assertion `Matches.size() == 1 && "Had duplicate keys to match on"' failed.

This depends on the fact that the method emitMatchRegisterName and in
particular the method EmitStringMatcherForChar found different registers
with the same names.

However, I have seen that this is quite common in many other backends
(sparca, mips, etc..).

Can somebody help me to figure out what is wrong with my code?

Thank you,
Edo
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