[llvm-dev] HW loads wider than int

[Jim Grosbach via llvm-dev]

Hi Alan,

ARM64 is like this. I suggest having a look at that backend (lib/Target/AArch64) and how it deals with implicit zeroing of the upper bits of the X registers.

-Jim

> On Jan 11, 2017, at 9:09 AM, Davis, Alan via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register.
> 
> So for a basic 'a = b + c' example, we get 
>  %0 = load i32, i32* @b, align 4, !tbaa !1
>  %1 = load i32, i32* @c, align 4, !tbaa !1
>  %add = add nsw i32 %1, %0
>  store i32 %add, i32* @a, align 4, !tbaa !1
> 
> And we'd want to generate
> ldw %r0, at b     ; load b (32 bits) from memory with sign extension to 64 bits
> ldw %r1, at c      ; load c (32 bits) from memory with sign extension to 64 bits
> addw %r2,%r0,%r1   ; add lower 32 bits of r0 and r1
> stw @a,%r2   ; store lower 32 bits of r2 to a
> 
> If I define the ldw instruction faithfully according to the HW, that is, extending to 64 bits, it won't match the load i32. Does that mean I will need to define both 32 and 64 bit versions (via a multiclass perhaps)? Or would I just define the true (64-bit) version and use a Pattern to map 32-bit loads to the true instruction? Or is there something that would be done in lowering? I tried this lowering action: 
>   setOperationAction(ISD::LOAD, MVT::i32, Promote);
> but got an assertion failure: "Can only promote loads to same size type"
> 
> Please forgive the elementary level of the question; we are just getting started and finding ISel a bit of a tough nut to crack.
> 
> -Alan  Davis
> 
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