[llvm-dev] Tweaking the Register Allocator's spill placement

[Johnson, Nicholas Paul via llvm-dev]

>> On Jan 9, 2017, at 2:55 PM, Johnson, Nicholas Paul via llvm-dev <llvm-
>dev at lists.llvm.org> wrote:
>> Note also how the register allocator unfortunately re-uses register r10.
>>This prevents Post-RA scheduling from helping.

Matthias wrote:
>The old post-ra-scheduler-list was using the
>{Aggressive|Critical}AntiDepBreaker classes to improve this sort of situation.
>They are not used for the MachinePostScheduler (I can only guess but
>possibly out of frustration of bugs and hard to understand code in the
>*DepBreakers). You could experiment with using those.

If I understand correctly, these dep breakers look for anti-dependences, then try to break them after the fact by renaming a register (assuming there is an available register).  Am investigating...

It seems that one could fix this before the fact, that is, discourage the register allocator from repeatedly choosing the same register (again assuming there are additional available registers). With luck, there would be fewer anti- and output-dependences because the adjacent live ranges would not share a common register.  

I imagine people have tried this and there is a good reason not to...

Thanks,
Nick Johnson
D. E. Shaw Research