[llvm-dev] Adding FP environment register modeling for constrained FP nodes

Tue Feb 14 12:16:53 PST 2017

> We should probably also enumerate what we're trying to do here. For example, I can't
> CSE (or hoist, etc.) a FP-operation across a call boundary that might change the
> rounding mode (if the call might change the rounding mode and the FP instructions
> read it) or if the call might query the FP environment (and the FP operations are
> tagged as writing it).

This is a very good point!

Having added implicit defs to the instructions that read and write the SEE FP control register (MXCSR), if I also add the implicit uses of that register by the FP operations (as you said PowerPC already has), then I won’t need to do anything to prevent code motion across function calls or instructions that change the rounding mode.

However, I also need to prevent code motion of FP operations relative to instructions that read the FP exception status.  I could accomplish this by modeling the fact that FP operations def the FP exception status, but I don’t want to inhibit code motion of FP operations relative to one another (at least not in the non-constrained case, and it’s probably not even necessary in the constrained case).  I think if I model the FP instructions as having a def but not a use of the status register that would do what I need it to.

I believe we agreed at the dev meeting that we don’t intend to guarantee the order in which FP operations are executed relative to when FP exceptions occur.

The SSE and later instructions introduce a slight wrinkle in that the same register is used (implicitly) for control and status, but I don’t see a reason why we couldn’t model it as two different registers since it isn’t referenced directly anyway.  Technically the FP instructions do read the exception status bits, but I think we can ignore that since they never clear bits, only set them.

So maybe I don’t need the constrained FP handling to do anything at all if the default handling can do all of the following without loss of performance:

-Model defs for instructions that write the FP control bits
-Model uses of the FP control bits for all FP operations
-Model defs of the FP status bits for all FP operations
-Model uses of the FP status bits for instructions that read them

Does that sound correct?

I think that only concern that would leave for constrained FP handling is that we need to make sure that no FP instructions are speculatively executed, but I don’t think the implicit def/use modeling would help with that anyway.  I’ve been operating on the assumption that it just doesn’t happen right now (which appears to be true), but I’m not sure there is anything that prevents it.

-Andy

From: Hal Finkel [mailto:hfinkel at anl.gov]
Sent: Tuesday, February 14, 2017 11:22 AM
To: Kaylor, Andrew <andrew.kaylor at intel.com>; llvm-dev at lists.llvm.org
Subject: Re: Adding FP environment register modeling for constrained FP nodes

On 02/14/2017 12:25 PM, Kaylor, Andrew wrote:
Hi Hal,

Thanks for the guidance.  I hope you don’t mind that I’m adding LLVMDev to this e-mail thread, as it seems as though it may be of general interest.

SGTM.

I agree that duplicating the FP opcodes should be our goal.  I just wasn’t sure that was entirely possible.  I’ll try adding implicit defs in the way you’ve suggested, but I’m concerned that there may be code that relies on the TII for that kind of thing -- for instance, InstrEmitter::EmitMachineNode() does this:

  bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;

where “NumDefs” comes from TII and “NumResults” comes from the node.  Obviously we can fix that up as needed, but it seems like a weak point in the design.  Perhaps it is still better than trying to maintain a duplicate set of opcodes though.

Good point. I think it is better to update (fix) code that does not handle dynamically-added implicit operands than trying to handle duplicated opcodes all over the place. FWIW, having code with InstrEmitter with this kind of assumption does not surprise me particularly (at that point in the pipeline, nothing else would have added any dynamic implicit defs yet).

I'm also happy to think about other ways to do this. We could have the instructions, by default, carry full dependencies and then relax them as desired (instead of the other way around).

We should probably also enumerate what we're trying to do here. For example, I can't CSE (or hoist, etc.) a FP-operation across a call boundary that might change the rounding mode (if the call might change the rounding mode and the FP instructions read it) or if the call might query the FP environment (and the FP operations are tagged as writing it).

I’m still trying to piece together how to get the set of nodes to be updated from the SelectionDAG to the InstrEmitter.  I’m still learning my way around this code.

In any event, I can confirm that for X86 targets the control register uses are not currently modeled.  I just committed a patch yesterday adding the MXCSR register and updating the instructions that directly read and write it (but still implicitly so).  I suppose you are correct that there is no reason not to add uses of that register to the instructions that derive their rounding behavior from it and then the constrained FP intrinsics will just need to add implicit defs where needed.  I’ll also need to add the x87 control register as that isn’t modeled at all right now.

Makes sense to me.

Thanks,
Andy

From: Hal Finkel [mailto:hfinkel at anl.gov]
Sent: Friday, February 10, 2017 4:58 PM
To: Kaylor, Andrew <andrew.kaylor at intel.com><mailto:andrew.kaylor at intel.com>
Subject: Re: Adding FP environment register modeling for constrained FP nodes

On 02/09/2017 06:41 PM, Kaylor, Andrew wrote:
Hi Hal,

I’ve been trying to figure out enough of the instruction selection code to be able to attach implicit use/def information for DAG nodes that have been selected from constrained FP pseudo-ops.  You seemed to have a clear idea in your mind of how this could be done.  I had an idea for what I intended, but I didn’t really know how to do it.

As I’ve been digging in to this, it seems that my idea that the implicit register use was something I could just append to an existing node was incorrect.  If I understand correctly, the implicit register use often (if not always) comes from TargetInstrInfo queries based on the opcode.  If this is right, then I’d need to introduce a new machine opcode for any instruction that I wanted to have an implicit register use.  For instance, if we just mutated ISD::STRICT_FADD to ISD::FADD and Select changed that to X86::MULSDrm, then to attach implicit MXCSR use to that I’d need a new opcode (X86::MULSDrm_Strict) that behaves just like X86::MULSDrm but has the implicit MXCSR use/def information associated with it.

Does it sound like I’m understanding this correctly?

You're correct that implicit operands normally come from the instruction definitions, but you can add whatever other implicit operands you'd like. We often do this to handle calls, returns, etc. - we add implicit operands corresponding to parameters and return values.

My thought was that, in SelectionDAGISel::DoInstructionSelection, after the call to Select, Node should have been mutated to be the associated machine instruction. We can then have a target hook which then updates the node operands to also have the implicit register dependencies. However, that does not explain how to actually do that: At the MI level, you can always call addOperand to add another implicit operand. Adding implicit uses at the SDAG level is also straightforward (because you can mutate the node to have additional operands that you get by calling CurDAG->getRegister(...).

I think the easiest way to do this is to add a map of the nodes to which we need to add the extra operands, and then we can just add the additional operands at the MI level from InstrEmitter.cpp after we otherwise build the MI representation for the instruction.

If so, is there a simple way to create these duplicate opcodes?  I’m looking at .td files trying to figure it out and it’s looking like a can of worms.  Is there a way to do this from TableGen’s

I specifically want to do this without duplicating the opcodes if possible. Duplicating the opcodes requires a lot more code changes to the backends that I'd like to avoid.

CodeGenDAGPatterns::GenerateVariants()?

I’m also not sure I know what I’m doing with finding the nodes that need to be updated.  In the simplest case the FP node gets updated directly into a single machine opcode node, but I don’t think that always happens and I’m not sure I can even count on the original node not being deleted.  I’ve experimented with using a DAGUpdateListener, but I’m not sure that does everything I need it to.  Am I overthinking this?

I think you're on the right track. DAGUpdateListener seems like the right approach. ISel already uses these for other purposes, and this will allow to do track what has happened to the node being instruction-selected. You're correct that there might be more than one instruction created as a result, but I don't think that should be a problem because you should only need to modify the final instruction.

At least on PowerPC, all of the floating-point instructions are already given implicit (use) operands of RM (which stands for 'rounding mode', but is used to represent all of the FP-environment state). None of these instructions, however, define RM, so there are no dependencies created. I think that the target callback on PowerPC would just need to add an implicit register def of 'RM' to the "final" instruction representing any operation to create the necessary dependency relationships.

X86 might not have these implicit uses already?

I’m starting to wonder if it might be better to back out what I did in the ISel and just require target-specific pattern matching and whatever other implementation bits are needed.

On the good news side of things, I wrote a simple function pass to translate all FP operations into the constrained intrinsics and with that pass being run as early as possible I can successfully run some real-world programs with extensive FP usage.

Neat :-)

I imagined that the way we'd do this is by putting a mode into the IRBuilder where it will generate the intrinsics instead of the regular instructions (kind of like it has a mode in which it will add fast-math flags by default).

Thanks again,
Hal

Anyway, if you can offer any guidance and tell me whether or not I’m heading in the right direction I would be very grateful.

Thanks,
Andy

--

Hal Finkel

Lead, Compiler Technology and Programming Languages

Leadership Computing Facility

Argonne National Laboratory

--

Hal Finkel

Lead, Compiler Technology and Programming Languages

Leadership Computing Facility

Argonne National Laboratory
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