[llvm-dev] Canonical way to handle zero registers?

[Alex Bradbury via llvm-dev]

On 24 December 2017 at 04:43, Sean Silva via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Thanks, that sounds like it would work. Was this based on what any other
> target did? Or do any other targets take this approach?
>
> I just want to make sure that we don't already have a hook suitable for
> this. Overriding runOnFunction to run what could be described as just a
> "late SelectionDAG pass" sounds pretty intrusive. Do you remember other
> approaches that didn't work?

An obvious approach that doesn't work: just writing a pattern. This
causes assertions, seemingly as some code paths don't like the
introduction of a physical register.

At least AArch64, Lanai, and RISC-V handle the zero register in
TgtDAGToDAGISel::Select. Lanai also has a "-1" register and handles
that case in the same place.

Copying from LanaiDAGToDAGISel::Select:

  EVT VT = Node->getValueType(0);
  switch (Opcode) {
  case ISD::Constant:
    if (VT == MVT::i32) {
      ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
      // Materialize zero constants as copies from R0. This allows the coalescer
      // to propagate these into other instructions.
      if (ConstNode->isNullValue()) {
        SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
                                             SDLoc(Node), Lanai::R0, MVT::i32);
        return ReplaceNode(Node, New.getNode());
      }
      // Materialize all ones constants as copies from R1. This allows the
      // coalescer to propagate these into other instructions.
      if (ConstNode->isAllOnesValue()) {
        SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
                                             SDLoc(Node), Lanai::R1, MVT::i32);
        return ReplaceNode(Node, New.getNode());
      }
    }
    break;



Best,

Alex