[llvm-dev] How to implement lowerReturn for poring GlobalISel to RISCV?

[Leslie Zhai via llvm-dev]

Hi LLVM developers,

Thank Daniel Sanders, Aditya Nandakumar and Justin Bogner's Tutorial[1]: 
Head First into GlobalISel about how to port, and Aditya took BPF target 
as a simple instance:


bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                   const Value *Val, unsigned VReg) const {
   assert(!Val == !VReg && "Return value without a vreg");
   MIRBuilder.buildInstr(BPF::RET);
   return true;
}


But how to implement it for RISCV target? 
https://github.com/xiangzhai/llvm/commit/c49146edbbf655e97727e22e4a87a020fb8da6e5

Because there are separate trap return instructions[2] per privilege 
level: MRET, SRET, and URET. MRET is always provided, while SRET must be 
provided if supervisor mode is supported. URET is only provided if 
user-mode traps are supported. and David added RISCV privileged 
instructionsit[3], then merged into upstream, it might be more complex 
than ARM[4] please give me some hint, thanks a lot!

[1] http://llvm.org/devmtg/2017-10/#tutorial2

[2] 
https://github.com/riscv/riscv-isa-manual/blob/master/src/machine.tex#L539

[3] https://reviews.llvm.org/D40383

[4] 
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMCallLowering.cpp#L280

-- 
Regards,
Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/