[llvm-dev] [GlobalISel] gen-global-isel failed to work

Daniel Sanders via llvm-dev llvm-dev at lists.llvm.org
Wed Dec 20 09:51:44 PST 2017 

TableGen expects there to be a member called STI so you can't rename it but you could add Subtarget and initialize it to STI to get things working quickly. Later on, you can try to remove Subtarget again by changing the ImmLeaf predicates that need it.

Alternatively, I suppose we could have TableGen provide Subtarget as an alias. It would be a fairly small and useful change to make if it turns out we have a lot of these predicates.

> On 20 Dec 2017, at 16:14, Leslie Zhai <lesliezhai at llvm.org.cn> wrote:
> 
> Sorry for my stupid... but after renamed `STI` to `Subtarget` https://github.com/xiangzhai/llvm/commit/819cd634157644146ce91a834bdc23e9301d93b1
> 
> it looked for `STI` again?
> 
> 
> [ 48%] Building CXX object lib/Target/RISCV/CMakeFiles/LLVMRISCVCodeGen.dir/RISCVInstructionSelector.cpp.o
> In file included from /data/project/xiangzhai/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp:97:
> /data/project/xiangzhai/llvm/build/lib/Target/RISCV/RISCVGenGlobalISel.inc:191:65: error: use of
>       undeclared identifier 'STI'
>   AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
>                                                                 ^
> 
> 
> Please give me some hint, thanks a lot!
> 
> 
> 在 2017年12月20日 22:46, Daniel Sanders 写道:
>> 
>> 
>>> On 20 Dec 2017, at 10:35, Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>> 
>>> 
>>> 
>>>> On 20 Dec 2017, at 10:25, Diana Picus <diana.picus at linaro.org <mailto:diana.picus at linaro.org>> wrote:
>>>> 
>>>> Hi Leslie,
>>>> 
>>>> On 20 December 2017 at 10:51, Leslie Zhai via llvm-dev
>>>> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>>>> Sorry, I am apprentice of lowRISC, and meet new bug when porting GlobalISel
>>>>> to RISCV target
>>>>> https://github.com/xiangzhai/llvm/commit/b3f91ea54d9fee0ef7e73a32c6b8456bbe252811
>>>>> 
>>>>> 
>>>>> In file included from
>>>>> /data/project/xiangzhai/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp:97:
>>>>> /data/project/xiangzhai/llvm/build/lib/Target/RISCV/RISCVGenGlobalISel.inc:100:7:
>>>>> error: use of
>>>>>     undeclared identifier 'Subtarget'
>>>>> if (Subtarget->is64Bit())
>>>>>     ^
>>>>> 
>>>>> 
>>>>> Even if no errors after comment `if (Subtarget->is64Bit())` in
>>>>> RISCVInstrInfo.td, but it is monkey patch, and it can't handle riscv64
>>>>> without the if condition check.
>>>>> 
>>>>> And I noticed there is `if (Subtarget->useMovt(*MF))` in ARMInstrInfo.td too
>>>>> https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMInstrInfo.td#L694
>>>> 
>>>> I haven't looked into this, but I would imagine that none of the
>>>> patterns using that are supported yet, and that's why we don't see any
>>>> errors for ARM yet.
>>>> 
>>>>> How ARM handle this? and I removed all ARM related code in RISCVXXX.cpp,
>>>>> only keep skeleton for easy debug, please give me some hint, thanks a lot!
>>>> 
>>>> ARMInstructionSelector has an ARMSubtarget reference called STI. We'll
>>>> probably have to rename that to Subtarget to support something like
>>>> this in the future.
>>>> 
>>>> What you need to do when you run into this kind of error is to add the
>>>> relevant members to your InstructionSelector. Each target may make
>>>> slightly different assumptions about what exists in the
>>>> InstructionSelector. This one is pretty obvious from the name, but in
>>>> the general case you might have to look at what exists in DAGISel.
>>> 
>>> Unfortunately, adding the members to InstructionSelector isn't going to work in this case. The ImmLeaf predicates are currently static functions and only have access to the immediate being tested. We're going to have to change how these predicates are generated to give them access to the members of the InstructionSelector.
>> 
>> I've fixed this limitation in r321176 by making the predicate functions members of the <Target>InstructionSelector. Starting from that commit, you can resolve the problem with referencing
>> Subtarget by adding it to the RISCVInstructionSelector as Diana suggested.
>> 
>>>> Hope that helps,
>>>> Diana
>>>> 
>>>>> 
>>>>> 在 2017年12月19日 21:28, Daniel Sanders 写道:
>>>>>> 
>>>>>> Sorry, I've given you the wrong header. The one I gave you does include
>>>>>> AVRGenRegisterInfo.inc but doesn't define the enum because it uses the wrong
>>>>>> macros for that. The correct one is '#include
>>>>>> "MCTargetDesc/AVRMCTargetDesc.h"'. You'll also need to 'include
>>>>>> "AVRRegisterBanks.td"' somewhere in your .td files. At the moment, your
>>>>>> register banks definitions aren't being used.
>>>>>> 
>>>>>>> On 19 Dec 2017, at 13:08, Leslie Zhai <lesliezhai at llvm.org.cn <mailto:lesliezhai at llvm.org.cn>> wrote:
>>>>>>> 
>>>>>>> Hi Daniel,
>>>>>>> 
>>>>>>> Thanks for your response!
>>>>>>> 
>>>>>>> 
>>>>>>> 在 2017年12月19日 18:53, Daniel Sanders 写道:
>>>>>>>> 
>>>>>>>> Hi Leslie,
>>>>>>>> 
>>>>>>>> There should be a definition of GPR8RegClassID in
>>>>>>>> $build_dir/lib/Target/AVR/AVRGenRegisterInfo.inc which should be included by
>>>>>>>> AVRRegisterInfo.h. AArch64 includes its AArch64RegisterInfo.h in
>>>>>>>> AArch64InstructionSelector.cpp but it seems that ARM gets it indirectly when
>>>>>>>> it includes ARMSubtarget.h. It looks like you need to add '#include
>>>>>>>> "AVRRegisterInfo.h"' to AVRInstructionSelector.h.
>>>>>>>> 
>>>>>>>> Hope that helps
>>>>>>> 
>>>>>>> Still failed to work :(
>>>>>>> https://github.com/xiangzhai/llvm/commit/1fc76db7f6fda156d2d0a2bafa6d8ea4c43a7e40
>>>>>>> It must be my stupid bug... I need to read the Resources more carefully!
>>>>>>> http://llvm.org/docs/GlobalISel.html
>>>>>>> 
>>>>>>> 
>>>>>>>>> On 19 Dec 2017, at 09:36, Leslie Zhai via llvm-dev
>>>>>>>>> <llvm-dev at lists.llvm.org> wrote:
>>>>>>>>> 
>>>>>>>>> Hi LLVM developers,
>>>>>>>>> 
>>>>>>>>> I am porting GlobalISel to AVR Target, try to delete SelectionDAG in
>>>>>>>>> 100* commits :) https://github.com/xiangzhai/llvm/tree/avr/lib/Target/AVR
>>>>>>>>> 
>>>>>>>>> I just copy ARMCallLowering, ARMRegisterBankInfo, ARMLegalizerInfo,
>>>>>>>>> ARMInstructionSelector, ARMRegisterBanks.td into AVR target's folder, then
>>>>>>>>> renamed them to AVRXXX
>>>>>>>>> 
>>>>>>>>> Removed ARM related code, for example:
>>>>>>>>> 
>>>>>>>>> * AEABI (eabi)
>>>>>>>>> 
>>>>>>>>> * hasDivideInXXXMode
>>>>>>>>> 
>>>>>>>>> * useSoftFloat (soft-float-point), hasVFP2
>>>>>>>>> 
>>>>>>>>> Overrided addIRTranslator, addLegalizeMachineIR,
>>>>>>>>> addRegBankSelectaddGlobalInstructionSelect in AVRTargetMachine.
>>>>>>>>> 
>>>>>>>>> Added AVRGenGlobalISel.inc to CMakeLists.txt for tablegen, also *.cpp
>>>>>>>>> related to GlobalISel.
>>>>>>>>> 
>>>>>>>>> Also added GlobalISel dependence to LLVMBuild.txt
>>>>>>>>> 
>>>>>>>>> But tablegen is failed to generate AVRGenGlobalISel.inc:
>>>>>>>>> 
>>>>>>>>> 
>>>>>>>>> [ 53%] Building CXX object
>>>>>>>>> lib/Target/AVR/CMakeFiles/LLVMAVRCodeGen.dir/AVRLegalizerInfo.cpp.o
>>>>>>>>> In file included from
>>>>>>>>> /data/project/xiangzhai/llvm/lib/Target/AVR/AVRInstructionSelector.cpp:103:
>>>>>>>>> 
>>>>>>>>> /data/project/xiangzhai/llvm/build/lib/Target/AVR/AVRGenGlobalISel.inc:112:64:
>>>>>>>>> error: no member named
>>>>>>>>>      'GPR8RegClassID' in namespace 'llvm::AVR'; did you mean
>>>>>>>>> 'GPR8RegClass'?
>>>>>>>>>        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0,
>>>>>>>>> /*RC*/AVR::GPR8RegClassID,
>>>>>>>>> ~~~~~^~~~~~~~~~~~~~
>>>>>>>>> GPR8RegClass
>>>>>>>>> 
>>>>>>>>> /data/project/xiangzhai/llvm/build/lib/Target/AVR/AVRGenRegisterInfo.inc:827:36:
>>>>>>>>> note: 'GPR8RegClass'
>>>>>>>>>      declared here
>>>>>>>>>  extern const TargetRegisterClass GPR8RegClass;
>>>>>>>>>                                   ^
>>>>>>>>> 
>>>>>>>>> 
>>>>>>>>> The general purpose registers, such as GPR8, defined in
>>>>>>>>> AVRRegisterInfo.td like this
>>>>>>>>> https://github.com/xiangzhai/llvm/blob/avr/lib/Target/AVR/AVRRegisterInfo.td#L114
>>>>>>>>> 
>>>>>>>>> Why auto-generated GPR8RegClassID, but not GPR8RegClass, where is the
>>>>>>>>> ID come from? please give me some hint, thanks a lot!
>>>>>>>>> 
>>>>>>>>> --
>>>>>>>>> Regards,
>>>>>>>>> Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/
>>>>>>>>> 
>>>>>>>>> 
>>>>>>>>> 
>>>>>>>>> _______________________________________________
>>>>>>>>> LLVM Developers mailing list
>>>>>>>>> llvm-dev at lists.llvm.org
>>>>>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>>>>>> 
>>>>>>> --
>>>>>>> Regards,
>>>>>>> Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/
>>>>>>> 
>>>>>>> 
>>>>>>> 
>>>>> 
>>>>> --
>>>>> Regards,
>>>>> Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/
>>>>> 
>>>>> 
>>>>> 
>>>>> _______________________________________________
>>>>> LLVM Developers mailing list
>>>>> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
>>>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>> 
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>> 
> 
> -- 
> Regards,
> Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/
> 
> 
>

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