[llvm-dev] New x86 instruction with opcode 0x0F 0x7A

[Barbora Murinová via llvm-dev]

Hi all,

I'm trying to simulate an extended x86 architecture on gem5 with several
new instructions. My hardware setup is done and now I'd like llvm to accept
the existence of the new instruction passed in inline assembly and output
the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and
I would like the instruction to have the same operands and return values
as CVTPS2PI instruction.

I have found this link (https://llvm.org/docs/ExtendingLLVM.html) which
claims "Before you invest a significant amount of effort into a non-trivial
extension, *ask on the list*" so that's what I'm doing. I would like to
know which of the solutions would work in my case and what's the easiest
way to achieve my goal.

Thank you very much!

-- 
----------------
Barbora Murinová
The University of Edinburgh
SK: +421905718390
UK: +447477833795
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