[llvm-dev] Query regarding LLVM IR is SSA

[Daniel Berlin via llvm-dev]

The load/store form is in fact in SSA. As you can see, each value is only
assigned once.
Memory is never in a strict SSA form in just about any compiler, because it
requires knowing, statically, what a load/store may actually affect.  That
is statically undecidable.

mem2reg is taking some of the memory operations where it can figure out
that they are safe to not be in memory,  and converting them to non-memory
operations.
In doing so, it is taking what was previously memory operations in ssa, and
converting them to register-like operations in ssa.

Both are still SSA.  One just looks more like the SSA you seem to expect.




On Tue, Dec 5, 2017 at 8:41 PM gurbani dimpal via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> I read in LLVM language reference manual that LLVM IR is in SSA Form, but
> when i compiled it using clang, it is giving me the below form which i
> can't see in SSA form and even i found that there is a pass -mem2reg to
> convert it into SSA form. Then, i am unable to understand that why it's
> written in manual that it is in SSA form. I feel if it is in SSA then we
> should not need to convert it. Could you please clarify my doubt, i am
> stuck here.
>
> .c Program:
>
> int main() {
>     int a=0, b=1, p=2, q=3, x, y, m, n, g;
>     if (m > n) {
>         x = a;
>         y = b;
>     }
>     else {
>         x = p;
>         y = q;
>     }
>     g = x + y;
>     return 0;
> }
>
> .ll Program:
>
> define i32 @main() #0 {
>   %1 = alloca i32, align 4
>   %a = alloca i32, align 4
>   %b = alloca i32, align 4
>   %p = alloca i32, align 4
>   %q = alloca i32, align 4
>   %x = alloca i32, align 4
>   %y = alloca i32, align 4
>   %m = alloca i32, align 4
>   %n = alloca i32, align 4
>   %g = alloca i32, align 4
>   store i32 0, i32* %1, align 4
>   store i32 0, i32* %a, align 4
>   store i32 1, i32* %b, align 4
>   store i32 2, i32* %p, align 4
>   store i32 3, i32* %q, align 4
>   %2 = load i32, i32* %m, align 4
>   %3 = load i32, i32* %n, align 4
>   %4 = icmp sgt i32 %2, %3
>   br i1 %4, label %5, label %8
>
> ; <label>:5                                       ; preds = %0
>   %6 = load i32, i32* %a, align 4
>   store i32 %6, i32* %x, align 4
>   %7 = load i32, i32* %b, align 4
>   store i32 %7, i32* %y, align 4
>   br label %11
>
> ; <label>:8                                       ; preds = %0
>   %9 = load i32, i32* %p, align 4
>   store i32 %9, i32* %x, align 4
>   %10 = load i32, i32* %q, align 4
>   store i32 %10, i32* %y, align 4
>   br label %11
>
> ; <label>:11                                      ; preds = %8, %5
>   %12 = load i32, i32* %x, align 4
>   %13 = load i32, i32* %y, align 4
>   %14 = add nsw i32 %12, %13
>   store i32 %14, i32* %g, align 4
>   ret i32 0
> }
>
> --
> Thanks and Regards,
> Dimpal Gurabani
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
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