[llvm-dev] [AMDGPU] Strange results with different address spaces

[Matt Arsenault via llvm-dev]

> On Dec 5, 2017, at 13:53, Matt Arsenault <arsenm2 at gmail.com> wrote:
> 
> 
> 
>> On Dec 5, 2017, at 02:51, Haidl, Michael via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>> 
>> Hi dev list, 
>> 
>> I am currently exploring the integration of AMDGPU/ROCm into the PACXX project and observing some strange behavior of the AMDGPU backend. The following IR is generated for a simple address space test that copies from global to shared memory and back to global after a barrier synchronization. 
>> 
>> Here is the IR is attached as as1.ll
>> 
>> The output is as follows: 
>> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 144 144 144 144 144 144 144 144 144 144 144 144 144 144 144 144 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 160 176 176 176 176 176 176 176 176 176 176 176 176 176 176 176 176 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 208 208 208 208 208 208 208 208 208 208 208 208 208 208 208 208 224 224 224 224 224 224 224 224 224 224 224 224 224 224 224 224 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
> 
> It looks like the addressing in as1.ll is incorrectly concluded to be uniform:
> 
>   %6 = tail call i32 @llvm.amdgcn.workitem.id.x() #0, !range !11
>   %7 = tail call i32 @llvm.amdgcn.workgroup.id.x() #0
>   %mul.i.i.i.i.i = mul nsw i32 %7, %3
>   %add.i.i.i.i.i = add nsw i32 %mul.i.i.i.i.i, %6
>   %idxprom.i.i.i = sext i32 %add.i.i.i.i.i to i64
>   %8 = getelementptr i32, i32 addrspace(1)* %callable.coerce0, i64 %idxprom.i.i.i, !amdgpu.uniform !12, !amdgpu.noclobber !12
> 
> However since this depends on workitem.id <http://workitem.id/>.x, it certainly is not
> 
> -Matt

Actually you have the amdgpu.uniform annotation already here, and it isn’t added by the backend optimization pass, so there’s a bug in however you produced this. It just happens the uniform load optimization doesn’t trigger on flat loads.

-Matt
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