[llvm-dev] Schedules, latency and register liveness for complex instructions

[Leslie Zhai via llvm-dev]

Hi Martin,

 > The CPU that I am targeting is VLIW with no hardware interlocking 
(the next instruction does not wait for the previous to complete). This 
leads to fairly complex scheduling, but can be generally accommodated 
well in LLVM.


Thanks for sharing your usecase about instruction scheduling, I am 
learning Instruction Selector by reading ARM and AMDGPU target's source 
code, then I will try to port GlobalISel to AVR target, and implement 
Scheduling definition. So I argue that AMDGPU's scheduler might give you 
some hint? 
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AMDGPU/R600Schedule.td 


-- 
Regards,
Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/