[llvm-dev] Need help with review: configurable register sizes in TableGen

Krzysztof Parzyszek via llvm-dev llvm-dev at lists.llvm.org
Tue Aug 29 09:08:41 PDT 2017

Hi All,

I've been working on implementing this feature for almost a year now. 
Here's a link to the original thread: 
Several people have expressed their interest in this work, and the 
actual development of it is complete at this point.

In April I posted a few patches for review, the shorter ones were 
committed, but the longer one is taking more time: 
In essence, it replaces TableGen's type inference to allow pattern 
matching in the presence of parametrized register classes.  In addition 
to that, it changes the emission of register class data to reflect the 

Several people have been helping with the reviewing, but due to the size 
of the patch (it's not easily reducible), it's probably hard to expect 
any individual person to review it entirely.

I'd like to get some general agreement that this patch can be committed 
(or comments about what can be improved before committing).  I'll be 
fixing any issues that come up.  This is the last chunk of code in this 
project that is still waiting for review.

I updated the review summary with the overview of the implementation 
(including rationale for various decisions).

I hope to get this committed soon.  A patch that utilizes this in 
Hexagon will follow shortly.


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