[llvm-dev] reg coalescing improvements

[Quentin Colombet via llvm-dev]

Hi Jonas,

> On Aug 17, 2017, at 3:52 AM, Jonas Paulsson via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hi,
> 
> I am seeing cases of poorly coalesced IV updates on SystemZ:
> 
> In the final IR, it is obvious that
> 
>       %R4D<def> = LA %R2D<kill>, 4, %noreg   // R4 = R2 + 4
>        %R2D<def> = LGR %R4D<kill>             // R2 = R4
> 
> could be optimized to ->
> 
>        %R2D<def> = LA %R2D<kill>, 4, %noreg   // R2 = R2 + 4
> 
> The reason this wasn't coalesced, is because of overlapping during coalescing:
> 
> 864B            %vreg11<def> = LA %vreg2, 4, %noreg
> 880B            %vreg16<def> = LLCMux %vreg2, 4, %noreg
> 928B            %vreg2<def>  = COPY %vreg11
> 
> It seems that if this had been rescheduled to
> 
> 880B            %vreg16<def> = LLCMux %vreg2, 4, %noreg
> 864B            %vreg11<def> = LA %vreg2, 4, %noreg
> 928B            %vreg2<def>  = COPY %vreg11
> 
> , %vreg11 and %vreg2 could have been coalesced (%vreg11 is unused outside this block)
> 
> My question is how to best handle this.
> 
> * Seems to me probably best to handle this pre-ra if possible, even though cases like this may be handled later.
> * Pre-RA mischeduler is run after the coalescer, so that's not going to work.

I may be optimistic but I would hope that reordering the instructions in mischeduler after the coalescer would allow regalloc to do the right thing, because the hints derived from the copy will be able to be satisfied.

Is that not the case?

Cheers,
-Quentin

> 
> thanks for any help,
> 
> Jonas
> 
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