[llvm-dev] reg alloc hints

[Jonas Paulsson via llvm-dev]

Hi,

I am curious if it would be possible to use reg-alloc hints to improve 
code generation for SystemZ. The background is that I ran into a 
regression which seems to relate to code generation for conditional 
register moves.

The SystemZ backend uses a GRX32 register class for a LOCRMux pseudo 
instroction (Load On Condition of Register), in order to utilize all 
32bit registers optimally. However, depending on the register assignment 
this pseudo will become a single load-on-condition instruction only if 
both source and dest registers are either low or high parts. Otherwise, 
LOCRMux will expand to a compare/jump sequence, which is of course less 
desirable. LOCR can only handle two low-parts, and LOCFHR can only 
handle two high-parts (GRX32 is the union of these two reg classes).

In order to increase the number of LOCR/LOCFHRs generated, I would like 
to tell regalloc something like  "If src reg of an LOCRMux is high, try 
to make dst reg high", and similarly for the case where one register is 
in the low part.

I am not sure if it is possible to do anything about this in a simple 
manner, and would appreciate any help.

Thanks,

Jonas